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CY2412SC-3 PDF预览

CY2412SC-3

更新时间: 2024-11-23 22:10:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟发生器石英晶振压控振荡器
页数 文件大小 规格书
6页 130K
描述
MPEG Clock Generator with VCXO

CY2412SC-3 数据手册

 浏览型号CY2412SC-3的Datasheet PDF文件第2页浏览型号CY2412SC-3的Datasheet PDF文件第3页浏览型号CY2412SC-3的Datasheet PDF文件第4页浏览型号CY2412SC-3的Datasheet PDF文件第5页浏览型号CY2412SC-3的Datasheet PDF文件第6页 
CY2412  
MPEG Clock Generator with VCXO  
Features  
Benefits  
• Integrated phase-locked loop (PLL)  
• Low-jitter, high-accuracy outputs  
• VCXO with analog adjust  
• 3.3V operation  
• Highest-performance PLL tailored for multimedia appli-  
cations  
• Meets critical timing requirements in complex system  
designs  
• Large ± 150-ppm range, better linearity  
• Enables application compatibility  
• 8-pin SOIC package  
Part Number  
Outputs  
Input Frequency Range  
Output Frequencies  
VCXO Profile  
CY2412-1  
3
13.5-MHz pullable crystal input per  
Two 27 MHz outputs, one 54 MHz (3.3V) Linear  
Cypress specification  
CY2412-3  
3
13.5-MHz pullable crystal input per  
Cypress specification  
27 MHz, 13.5 MHz, 54 MHz (3.3V)  
Linear  
Logic Block Diagram  
Pin Configuration  
CY2412-1,-3  
8-pin SOIC  
CLKC  
CLKB  
13.5 XIN  
OUTPUT  
DIVIDERS  
OSC  
Q
Φ
XOUT  
1
2
3
4
XOUT  
8
7
6
5
XIN  
VCO  
CLKC  
CLKB  
VDD  
VCXO  
VSS  
CLKA  
P
VCXO  
PLL  
CLKA  
VSS  
VDD  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07227 Rev. *D  
Revised December 13, 2004  

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