Datasheet > CY24130_08

CY24130_08

更新时间： 2022-10-24 11:38:33

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
6页	205K
描述
HOTLink II? SMPTE Receiver Training Clock

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数据手册

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CY24130_08 数据手册

CY24130

HOTLink II™ SMPTE Receiver Training

Clock

Features

Benefits

■ Integrated phase-locked loop

■ Low-jitter, high-accuracy outputs

■ 3.3V operation

■ Internal PLL with up to 400-MHz internal operation

■ Meets critical timing requirements in complex system

designs

■ Enables application compatibility

Table 1. Frequency table

Part Number Outputs

Input Frequency

27 MHz (Driven Reference) 1 copy 27-MHz reference clock output

1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable)

27 MHz (Crystal Reference) 1 copy 27-MHz reference clock output

Output Frequency Range

CY24130-1

CY24130-2

1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable)

Logic Block Diagram

XIN

OSC.

VCO

PLL

OUTPUT

MULTIPLEXER

AND

DIVIDERS

XOUT

CLKA

REFCLK

VSS

AVDD AVSS

VDDL VDD

VSSL

Table 2. Frequency Select Options

CLKA

REFCLK

Units

MHz

148.50

74.25

OFF, pulled low

Cypress Semiconductor Corporation

Document #: 38-07711 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 22, 2008

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与CY24130_08相关器件

型号	品牌	描述	获取价格	数据表
CY24130-1	CYPRESS	HOTLink SMPTE Receiver Training Clock	获取价格
CY24130-2	CYPRESS	HOTLink SMPTE Receiver Training Clock	获取价格
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