Datasheet > CY2300_08

CY2300_08

更新时间： 2024-11-29 06:51:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
6页	205K
描述
Phase-Aligned Clock Multiplier

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中文翻译

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数据手册

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CY2300_08 数据手册

CY2300

Phase-Aligned Clock Multiplier

Features

Benefits

■ 4-multiplier configuration

■ Single phase-locked loop architecture

■ Phase Alignment

■ 1/2x, 1x, 1x, 2x Ref

■ 10 MHz to 166.67 MHz operating range (reference input from

20 MHz to 83.33 MHz)

■ Alloutputshaveaconsistentphaserelationshipwitheachother

and the reference input

■ Low jitter, high accuracy outputs

■ Output enable pin

■ Meets critical timing requirements

■ 3.3V operation

■ Enables design flexibility and lower power

consumption

■ 5V Tolerant input

■ Supports industry standard design platforms

■ Allows flexibility on Reference input

■ Internal loop filter

■ 8-pin 150-mil SOIC package

■ Commercial Temperature

■ Alleviates the need for external components

■ Industry standard packaging saves on board space

■ Suitable for wide spectrum of applications

Logic Block Diagram

FBK

PLL

1/2xREF

REFIN

REF

Divider

Logic

REF

2xREF

Cypress Semiconductor Corporation

Document #: 38-07252 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 23, 2008

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与CY2300_08相关器件

型号	品牌	获取价格	描述	数据表
CY2300_12	CYPRESS	获取价格	Phase-Aligned Clock Multiplier
CY2300SC	CYPRESS	获取价格	Phase-Aligned Clock Multiplier
CY2300SI	CYPRESS	获取价格	Phase-Aligned Clock Multiplier
CY2300SIT	CYPRESS	获取价格	PLL Based Clock Driver, PDSO8, 0.150 INCH, PLASTIC, SOIC-8
CY2300SXC	CYPRESS	获取价格	Phase-Aligned Clock Multiplier
CY2300SXC	INFINEON	获取价格	3.3V 1:4 Zero Delay Buffer with /2 and X2 Function
CY2300SXCT	CYPRESS	获取价格	Phase-Aligned Clock Multiplier
CY2300SXCT	INFINEON	获取价格	3.3V 1:4 Zero Delay Buffer with /2 and X2 Function
CY2300SXIT	CYPRESS	获取价格	PLL Based Clock Driver, 2300 Series, PDSO8, 0.150 INCH, PLASTIC, SOIC-8
CY2302	CYPRESS	获取价格	Frequency Multiplier and Zero Delay Buffer