Datasheet > CY2300SXC

CY2300SXC

更新时间： 2023-12-06 20:08:18

品牌	Logo	应用领域
英飞凌 - INFINEON		/
页数	文件大小	规格书
13页	425K
描述
3.3V 1:4 Zero Delay Buffer with /2 and X2 Function

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CY2300SXC 数据手册

CY2300

Phase-Aligned Clock Multiplier

Features

Functional Description

■ 10 MHz to 166.67 MHz output operating range

■ Four-multiplier configuration

■ Single PLL architecture

The CY2300 is a four output 3.3 V phase-aligned system clock

designed to distribute high-speed clocks in PC, workstation,

datacom, telecom, and other high-performance applications.

The part allows the user to obtain 1/2x, 1x, 1x and 2x REFIN

output frequencies on respective output pins.

■ Phase aligned outputs

The part has an on-chip PLL which locks to an input clock

presented on the REFIN pin. The input-to-output skew is

guaranteed to be less than 200 ps, and output-to-output skew

is guaranteed to be less than 200 ps.

■ Low jitter, high accuracy outputs

■ Output enable pin

■ 3.3 V operation

Multiple CY2300 devices can accept the same input clock and

distribute it in a system. In this case, the skew between the

outputs of two devices is guaranteed to be less than 400 ps.

■ 5 V tolerant input

■ Internal loop filter

The CY2300 is available in commercial temperature range.

For a complete list of related documentation, click here.

■ 8-pin 150-mil small-outline integrated circuit (SOIC) package

■ Commercial temperature

Logic Block Diagram

FBK

1/2xREF

PLL

REFIN

REF

Divider

Logic

REF

2xREF

Cypress Semiconductor Corporation

Document Number: 38-07252 Rev. *J

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 2, 2018

12 3 4 5 6 7...13

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与CY2300SXC相关器件

型号	品牌	描述	获取价格	数据表
CY2300SXCT	CYPRESS	Phase-Aligned Clock Multiplier	获取价格
CY2300SXCT	INFINEON	3.3V 1:4 Zero Delay Buffer with /2 and X2 Function	获取价格
CY2300SXIT	CYPRESS	PLL Based Clock Driver, 2300 Series, PDSO8, 0.150 INCH, PLASTIC, SOIC-8	获取价格
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