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CY22050KZXC-XXXT PDF预览

CY22050KZXC-XXXT

更新时间: 2024-11-26 13:07:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟发生器PC
页数 文件大小 规格书
8页 177K
描述
Clock Generator, 200MHz, CMOS, PDSO16, 4.40 MM, LEAD FREE, MO-153, TSSOP-16

CY22050KZXC-XXXT 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:TSSOP包装说明:TSSOP, TSSOP16,.25
针数:16Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.26JESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:5 mm
湿度敏感等级:3端子数量:16
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:200 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:2.5/3.3,3.3 V
主时钟/晶体标称频率:133 MHz认证状态:Not Qualified
座面最大高度:1.1 mm子类别:Clock Generators
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

CY22050KZXC-XXXT 数据手册

 浏览型号CY22050KZXC-XXXT的Datasheet PDF文件第2页浏览型号CY22050KZXC-XXXT的Datasheet PDF文件第3页浏览型号CY22050KZXC-XXXT的Datasheet PDF文件第4页浏览型号CY22050KZXC-XXXT的Datasheet PDF文件第5页浏览型号CY22050KZXC-XXXT的Datasheet PDF文件第6页浏览型号CY22050KZXC-XXXT的Datasheet PDF文件第7页 
CY22800  
Universal Programmable Clock Generator  
(UPCG)  
Features  
Benefits  
• Spread Spectrum, VCXO, and Frequency Select  
• Input frequency range:  
• Make inventory of only one device, CY22800, to use in  
various applications such as HDTV, STB, DVDR, etc.  
• Multiple predefined configurations that can be programmed  
into a single chip  
— Crystal: 8–30 MHz  
— CLKIN: 0.5–100 MHz  
• Eliminates the need for expensive and difficult to use  
higher-order crystal  
• Output frequency:  
— LVCMOS: 1–200 MHz  
• Integrated phase-locked loop  
• Low jitter, high accuracy outputs  
• 3.3V operation  
• High-performance PLL tailored for multiple applications  
• Meets critical timing requirements in complex system  
designs  
• Enables application compatibility  
• Allows up to three different frequency selects  
• 8-pin SOIC package  
Logic Block Diagram  
Pin Configuration  
CY22800  
8-pin SOIC  
CLKC  
XIN/CLKIN  
OSC  
Q
Φ
XOUT  
1
2
3
4
XIN/CLKIN  
8
7
6
5
OUTPUT  
DIVIDER  
XOUT  
VCXO  
VCO  
CLKB  
CLKA  
CLKC/FS2/VSS  
CLKA/FS0  
VDD  
FS0/VCXO  
VSS  
P
FS2  
FS1  
FS0  
CLKB/FS1  
PLL  
(with modulation control)  
VSS  
VDD  
Pin Description  
Name  
Pin Number Description  
XIN  
1
2
3
4
5
6
7
8
Reference Input; Crystal or External Clock  
3.3V Voltage Supply  
Frequency Select 0/VCXO Analog Control Voltage[1]  
VDD  
FS0/VCXO  
VSS  
Ground  
CLKB/FS1  
CLKA/FS0  
CLKC/FS2/VSS  
XOUT  
Clock Output B/Frequency Select 1[1]  
Clock Output A/Frequency Select 0[1]  
Clock Output C/Frequency Select 2/VSS[1]  
Reference Output (No Connect when the reference is a clock)  
Note  
1. Pin definition changes for different configurations. Refer to the specific one-page data sheet for more details.  
Cypress Semiconductor Corporation  
Document #: 001-07704 Rev. **  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised July 14, 2006  

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