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CY2211QC-3 PDF预览

CY2211QC-3

更新时间: 2024-11-23 20:42:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
13页 156K
描述
PLL Based Clock Driver, 1 True Output(s), 1 Inverted Output(s), PDSO24, 0.150 INCH, QSOP-24

CY2211QC-3 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SSOP,针数:24
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.82输入调节:STANDARD
JESD-30 代码:R-PDSO-G24长度:8.65 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER功能数量:1
反相输出次数:1端子数量:24
实输出次数:1最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压 (Vsup):3.5 V最小供电电压 (Vsup):3.1 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
宽度:3.9116 mmBase Number Matches:1

CY2211QC-3 数据手册

 浏览型号CY2211QC-3的Datasheet PDF文件第2页浏览型号CY2211QC-3的Datasheet PDF文件第3页浏览型号CY2211QC-3的Datasheet PDF文件第4页浏览型号CY2211QC-3的Datasheet PDF文件第5页浏览型号CY2211QC-3的Datasheet PDF文件第6页浏览型号CY2211QC-3的Datasheet PDF文件第7页 
1
PRELIMINARY  
CY2211  
Direct Rambus™ Clock Generator  
Features  
Benefits  
• High-Speed Clock Support  
CY2211-2 “DRCG Plus” and CY2211-3 “DRCG III” provide a differen-  
tial clock source for Direct Rambus™ memory systems. The only dif-  
ference between the two parts is the PLL Divider Selections or “gear  
ratios” as specified on page 3.  
• Synchronization Flexibility  
• Power Management Support  
The CY2211 includes signals to synchronize the clock domains of the  
Rambus® Channel with an external system or processor clock.  
The CY2211 is able to turn off the Rambus Channel clock to minimize  
power for mobile and other power-sensitive applications:  
In the ‘Clk Stop’ mode, the CY2211 remains on while the output  
is disabled, allowing fast transitions between the clock-off and  
clock-on states. This mode could be used in conjunction with  
the Nap mode of the RDRAMs and Rambus ASIC Cell (RAC)  
In the ‘Power-down’ mode, the CY2211 is completely powered  
down for minimum power dissipation. This mode is used in con-  
junction with the power down modes of the RDRAMs and RAC.  
• Independent Channel Clocking Support  
The CY2211 supports systems that do not require synchronization of  
the Rambus clock to another system clock.  
• Low jitter outputs  
Meets tight system timing requirements at high frequency  
• 24-pin QSOP package (150-mil SSOP)  
Widely available, industry standard package enables lower cost  
Logic Block Diagram  
3
S [0:2]  
BYPCLK  
TEST  
DIVIDER  
TEST  
MUX  
CLK  
X
PLLCLK  
BYPASS  
MUX  
CLKB  
B
A
PHASE  
ALIGNER  
REFCLK  
PLL  
PACLK  
PHASE  
DETECTOR  
STOPB  
PCLKM  
2
2
SYNCLKN  
Pin Configuration  
MULT [0:1]  
PWRDWNB  
24-PIN QSOP  
TOP VIEW  
S0  
S1  
V
V
1
2
3
4
5
6
24  
23  
22  
21  
20  
19  
18  
17  
DDR  
REFCLK  
V
DDO  
DDC  
V
V
SS  
SS  
CLK  
N/C  
V
SS  
PCLKM  
SYNCLKN  
CLKB  
7
V
V
SS  
8
SS  
V
16  
15  
14  
13  
DDC  
9
V
DDO  
V
MULT0  
MULT1  
S2  
DDPD  
10  
11  
12  
STOPB  
PWRDWNB  
Direct Rambus is a trademark and Rambus is a registered trademark of Rambus, Inc.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
December 1, 1999, rev. A  

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