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CY2210PVC-4T PDF预览

CY2210PVC-4T

更新时间: 2024-09-16 17:46:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
9页 129K
描述
Processor Specific Clock Generator, 133.33MHz, CMOS, PDSO56, SSOP-56

CY2210PVC-4T 技术参数

生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:56
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.79
JESD-30 代码:R-PDSO-G56长度:18.415 mm
端子数量:56最高工作温度:70 °C
最低工作温度:最大输出时钟频率:133.33 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
主时钟/晶体标称频率:14.318 MHz认证状态:Not Qualified
座面最大高度:2.794 mm最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
宽度:7.5 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

CY2210PVC-4T 数据手册

 浏览型号CY2210PVC-4T的Datasheet PDF文件第2页浏览型号CY2210PVC-4T的Datasheet PDF文件第3页浏览型号CY2210PVC-4T的Datasheet PDF文件第4页浏览型号CY2210PVC-4T的Datasheet PDF文件第5页浏览型号CY2210PVC-4T的Datasheet PDF文件第6页浏览型号CY2210PVC-4T的Datasheet PDF文件第7页 
CY2210  
133-MHz Spread Spectrum Clock Synthesizer/Driver  
with AGP, USB, and DRCG Support  
Features  
Benefits  
• Mixed 2.5V and 3.3V Operation  
Usable with Pentium II and Pentium III processors  
• Compliant to Intel® CK133 (CY2210-3) & CK133W  
(CY2210-2) synthesizer and driver specification  
• Multiple output clocks at different frequencies  
— Four CPU clocks, up to 133 MHz  
Single-chip main motherboard clock generator  
— Driven together, support 4 CPUs and a chipset  
— Support for 4 PCI slots and chipset  
— Eight synchronous PCI clocks, 1 free-running  
— Two CPU/2 clocks, at one-half the CPU frequency  
— Four AGP clocks at 66 MHz  
— Drives up to two main memory clock generators, includ-  
ing DRCG (CPUCLK/2)  
— Support for multiple AGP slots  
— Three synchronous APIC clocks, at 16.67 MHz  
— One USB clock at 48 MHz  
— Support multiprocessing systems  
— Supports USB frequencies and I/O chip  
— Two reference clocks at 14.318 MHz  
• Spread Spectrum clocking  
Enables reduction of EMI in some systems  
— 32.5-kHz modulation frequency @ 133 MHz  
— 33.1-kHz modulation frequency @ 100 MHz for  
CY2210-02/03  
— 33.4-kHz modulation frequency @ 100 MHz for  
CY2210-04  
— EPROM programmable percentage of spreading.  
Default is –0.6%, which is recommended by Intel  
• Power-down features  
Supports mobile systems  
• Three Select inputs  
Supports up to eight CPU clock frequencies  
Meets tight system timing requirements at high frequency  
Enables ATE and “bed of nails” testing  
• Low-skew and low-jitter outputs  
• OE and Test Mode support  
• 56-pin SSOP package  
Widely available, standard package enables lower cost  
SSOP  
Top View  
Logic Block Diagram  
V
DDAPIC  
1
2
3
4
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
V
SSREF  
REFCLK [0–1] (14.318 MHz)  
CPUCLK [0–3]  
APICCLK2  
APICCLK1  
APICCLK0  
REFCLK0  
REFCLK1  
V
DDREF  
V
XTALIN  
5
6
SSAPIC  
V
XTALOUT  
V
CPU_STOP  
XTALIN  
DDCPU/2  
SSPCI  
CPUCLK/2  
(DRCG)  
7
PCICLK_F  
PCICLK1  
CPUCLK/2  
8
CPUCLK/2 [0–1] (DRCG)  
PCICLK_F (33.33 MHz)  
(DRCG)  
14.318  
MHz  
OSC.  
CPU  
PLL  
Divider,  
EPROM-Pr  
ogDelay  
and  
9
V
V
SSCPU/2  
DDCPU  
V
DDPCI  
10  
11  
XTALOUT  
PCICLK2  
PCICLK3  
CPUCLK3  
CPUCLK2  
Stop Logic  
12  
13  
SEL1  
SEL0  
SEL133  
V
V
PCICLK [1–7] (33.33 MHz)  
APICCLK [0–2] (16.67 MHz)  
AGPCLK [0–3] (66.67 MHz)  
SSCPU  
SSPCI  
EPROM  
V
14  
15  
16  
17  
18  
19  
20  
21  
PCICLK4  
PCICLK5  
DDCPU  
SPREAD  
CPUCLK1  
CPUCLK0  
V
DDPCI  
PCI_STOP  
PWR_DWN  
V
40  
39  
38  
PCICLK6  
PCICLK7  
SSCPU  
AV  
DD  
V
SSPCI  
AV  
SS  
V
SSAGP  
PCI_STOP  
37  
36  
35  
34  
SYS  
PLL  
USBCLK (48 MHz)  
AGPCLK0  
AGPCLK1  
CPU_STOP  
22  
23  
24  
25  
PWR_DWN  
SPREAD  
SEL1  
V
DDAGP  
V
33  
32  
31  
30  
29  
SSAGP  
AGPCLK2  
AGPCLK3  
SEL0  
V
26  
27  
28  
DDUSB  
V
DDAGP  
USBCLK  
SEL133  
V
SSUSB  
Intel and Pentium are registered trademarks of Intel Corporation.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
May 18, 2000, rev. *A  

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