Y2210
CY2210
133 MHz Spread Spectrum Clock Synthesizer/Driver
with AGP, USB, and DRCG Support
Features
Benefits
Usable with Pentium® II and Pentium® III processors
• Mixed 2.5V and 3.3V Operation
• Compliant to Intel® CK133 (CY2210-3) & CK133W
(CY2210-2) synthesizer and driver specification
• Multiple output clocks at different frequencies
— Four CPU clocks, up to 133 MHz
Single-chip main motherboard clock generator
— Driven together, support 4 CPUs and a chipset
— Support for 4 PCI slots and chipset
— Eight synchronous PCI clocks, 1 free-running
— Two CPU/2 clocks, at one-half the CPU frequency
— Four AGP clocks at 66 MHz
— Drivesuptotwomainmemoryclockgenerators, including
DRCG (CPUCLK/2)
— Support for multiple AGP slots
— Three synchronous APIC clocks, at 16.67 MHz
— One USB clock at 48 MHz
— Support multiprocessing systems
— Supports USB frequencies and I/O chip
— Two reference clocks at 14.318 MHz
• Spread Spectrum clocking
Enables reduction of EMI in some systems
— 32.5-kHz modulation frequency @ 133 MHz
— 33.1-kHz modulation frequency @ 100 MHz for
CY2210-02/03
— 33.4-kHz modulation frequency @ 100 MHz for
CY2210-04
— EPROM programmable percentage of spreading. Default
is –0.6%, which is recommended by Intel
• Power-down features
Supports mobile systems
• Three Select inputs
Supports up to eight CPU clock frequencies
Meets tight system timing requirements at high frequency
Enables ATE and “bed of nails” testing
• Low-skew and low-jitter outputs
• OE and Test Mode support
• 56-pin SSOP package
Widely available, standard package enables lower cost
Pin Configuration
Top View
Logic Block Diagram
V
DDAPIC
REFCLK [0–1] (14.318 MHz)
CPUCLK [0–3]
1
2
3
4
56
55
54
V
SSREF
APICCLK2
APICCLK1
APICCLK0
REFCLK0
REFCLK1
V
53
52
51
50
DDREF
V
5
6
XTALIN
SSAPIC
CPU_STOP
XTALOUT
V
DDCPU/2
V
CPUCLK/2
(DRCG)
SSPCI
7
PCICLK_F
PCICLK1
CPUCLK/2 [0–1] (DRCG)
PCICLK_F (33.33 MHz)
49
48
47
46
CPUCLK/2
(DRCG)
SSCPU/2
8
XTALIN
14.318
CPU
9
V
MHz
Divider,
PLL
OSC.
V
V
DDPCI
XTALOUT
DDCPU
10
11
EPRO
PCICLK2
PCICLK3
CPUCLK3
CPUCLK2
45
44
43
SEL1
SEL0
SEL133
SPREAD
12
13
M-
PCICLK [1–7] (33.33 MHz)
APICCLK [0–2] (16.67 MHz)
AGPCLK [0–3] (66.67 MHz)
V
V
SSCPU
SSPCI
EPROM
V
14
15
16
17
18
PCICLK4
PCICLK5
DDCPU
42
41
CPUCLK1
CPUCLK0
V
DDPCI
PCI_STOP
PWR_DWN
V
40
39
38
PCICLK6
PCICLK7
SSCPU
AV
DD
V
19
20
21
22
23
AV
SS
SSPCI
V
PCI_STOP
SSAGP
37
36
35
34
SYS
PLL
USBCLK (48 MHz)
AGPCLK0
AGPCLK1
CPU_STOP
PWR_DWN
SPREAD
SEL1
V
DDAGP
V
33
32
31
30
29
SSAGP
24
25
AGPCLK2
AGPCLK3
SEL0
V
26
27
28
DDUSB
V
DDAGP
USBCLK
SEL133
V
SSUSB
Rev 1.0, November 25, 2006
Page 1 of 10
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555 Fax:(408) 855-0550
www.SpectraLinear.com