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CY2210

更新时间： 2024-11-05 22:10:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 驱动器时钟
页数 文件大小 规格书
10页 132K
描述
133-MHz Spread Spectrum Clock Synthesizer/Driver with AGP, USB, and DRCG Support

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中文翻译

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CY2210 数据手册

 浏览型号CY2210的Datasheet PDF文件第2页浏览型号CY2210的Datasheet PDF文件第3页浏览型号CY2210的Datasheet PDF文件第4页浏览型号CY2210的Datasheet PDF文件第5页浏览型号CY2210的Datasheet PDF文件第6页浏览型号CY2210的Datasheet PDF文件第7页 
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CY2210  
133-MHz Spread Spectrum Clock Synthesizer/Driver  
with AGP, USB, and DRCG Support  
Features  
Benefits  
• Mixed 2.5V and 3.3V Operation  
Usable with Pentium® II and Pentium® III processors  
• Compliant to Intel® CK133 (CY2210-3) & CK133W  
(CY2210-2) synthesizer and driver specification  
• Multiple output clocks at different frequencies  
—Four CPU clocks, up to 133 MHz  
Single-chip main motherboard clock generator  
—Driven together, support 4 CPUs and a chipset  
—Support for 4 PCI slots and chipset  
—Eight synchronous PCI clocks, 1 free-running  
—Two CPU/2 clocks, at one-half the CPU frequency  
—Four AGP clocks at 66 MHz  
—Drives up to two main memory clock generators, includ-  
ing DRCG (CPUCLK/2)  
—Support for multiple AGP slots  
—Three synchronous APIC clocks, at 16.67 MHz  
—One USB clock at 48 MHz  
—Support multiprocessing systems  
—Supports USB frequencies and I/O chip  
—Two reference clocks at 14.318 MHz  
• Spread Spectrum clocking  
Enables reduction of EMI in some systems  
—32.5-kHz modulation frequency @ 133 MHz  
—33.1-kHz modulation frequency @ 100 MHz for  
CY2210-02/03  
—33.4-kHz modulation frequency @ 100 MHz for  
CY2210-04  
—EPROM programmable percentage of spreading.  
Default is –0.6%, which is recommended by Intel  
• Power-down features  
Supports mobile systems  
• Three Select inputs  
Supports up to eight CPU clock frequencies  
Meets tight system timing requirements at high frequency  
Enables ATE and “bed of nails” testing  
• Low-skew and low-jitter outputs  
• OE and Test Mode support  
• 56-pin SSOP package  
Widely available, standard package enables lower cost  
Logic Block Diagram  
Pin Configuration  
SSOP  
Top View  
VDDAPIC  
REFCLK [0–1] (14.318 MHz)  
CPUCLK [0–3]  
1
2
3
4
56  
55  
54  
VSSREF  
APICCLK2  
APICCLK1  
APICCLK0  
VSSAPIC  
REFCLK0  
REFCLK1  
VDDREF  
53  
52  
51  
50  
XTALIN  
5
6
CPU_STOP  
XTALOUT  
VSSPCI  
VDDCPU/2  
CPUCLK/2  
(DRCG)  
7
CPUCLK/2 [0–1] (DRCG)  
PCICLK_F  
PCICLK1  
VDDPCI  
49  
48  
47  
46  
45  
44  
43  
42  
41  
CPUCLK/2  
(DRCG)  
8
XTALIN  
14.318  
MHz  
OSC.  
CPU  
PLL  
Divider,  
EPROM-  
ProgDelay  
and  
9
VSSCPU/2  
XTALOUT  
VDDCPU  
10  
11  
PCICLK_F (33.33 MHz)  
PCICLK2  
PCICLK3  
CPUCLK3  
CPUCLK2  
VSSCPU  
Stop Logic  
SEL1  
SEL0  
SEL133  
12  
13  
PCICLK [1–7] (33.33 MHz)  
APICCLK [0–2] (16.67 MHz)  
AGPCLK [0–3] (66.67 MHz)  
VSSPCI  
PCICLK4  
PCICLK5  
VDDPCI  
EPROM  
VDDCPU  
14  
15  
16  
17  
18  
19  
20  
SPREAD  
CPUCLK1  
CPUCLK0  
VSSCPU  
PCI_STOP  
PWR_DWN  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
PCICLK6  
PCICLK7  
AVDD  
VSSPCI  
AVSS  
SYS  
PLL  
VSSAGP  
USBCLK (48 MHz)  
PCI_STOP  
AGPCLK0  
CPU_STOP  
21  
22  
23  
24  
25  
26  
27  
28  
AGPCLK1  
VDDAGP  
PWR_DWN  
SPREAD  
SEL1  
VSSAGP  
AGPCLK2  
AGPCLK3  
VDDAGP  
SEL0  
VDDUSB  
USBCLK  
VSSUSB  
30  
29  
SEL133  
Intel and Pentium are registered trademarks of Intel Corporation.  
Cypress Semiconductor Corporation  
Document #: 38-07204 Rev. *A  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Revised December 14, 2002  
1234567...10

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