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CY2211QC-1 PDF预览

CY2211QC-1

更新时间: 2024-11-06 19:59:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟光电二极管外围集成电路
页数 文件大小 规格书
13页 717K
描述
Processor Specific Clock Generator, 100MHz, CMOS, PDSO24, 0.150 INCH, QSOP-24

CY2211QC-1 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:0.150 INCH, QSOP-24针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.85
JESD-30 代码:R-PDSO-G24JESD-609代码:e0
长度:8.65 mm湿度敏感等级:1
端子数量:24最高工作温度:70 °C
最低工作温度:最大输出时钟频率:100 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP24,.24封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):240
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Clock Generators
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

CY2211QC-1 数据手册

 浏览型号CY2211QC-1的Datasheet PDF文件第2页浏览型号CY2211QC-1的Datasheet PDF文件第3页浏览型号CY2211QC-1的Datasheet PDF文件第4页浏览型号CY2211QC-1的Datasheet PDF文件第5页浏览型号CY2211QC-1的Datasheet PDF文件第6页浏览型号CY2211QC-1的Datasheet PDF文件第7页 
PRELIMINARY  
CY2211  
®
Direct Rambus Clock Generator  
Features  
Benefits  
• High Speed Clock Support  
Provides 400-MHz differential clock source for Direct Rambus mem-  
ory systems for an 800-MHz data transfer rate.  
Synchronization Flexibility  
The CY2211 includes signals to synchronize the clock domains of the  
Rambus® Channel with an external system or processor clock.  
• Power Management Support  
The CY2211 is able to turn off the Rambus Channel clock to minimize  
power for mobile and other power-sensitive applications:  
IntheCLKStopmode, theCY2211remainsonwhiletheoutput  
is disabled, allowing fast transitions between the clock-off and  
clock-on states. This mode could be used in conjunction with  
the Nap mode of the RDRAMs and Rambus ASIC Cell (RAC)  
In the ‘Powerdown’ mode, the CY2211 is completely powered  
down for minimum power dissipation. This mode is used in con-  
junction with the power down modes of the RDRAMs and RAC.  
• Independent Channel Clocking Support  
The CY2211 supports systems that do not require synchronization of  
the Rambus clock to another system clock.  
• Low Jitter Outputs  
Meets tight system timing requirements at high frequency.  
• 24-pin QSOP Package (150-mil SSOP)  
Widely available, industry standard package enables lower cost.  
Logic Block Diagram  
3
S [0:2]  
BYPCLK  
TEST  
DIVIDER  
TEST  
MUX  
CLK  
X
PLLCLK  
BYPASS  
MUX  
CLKB  
REFCLK  
B
A
PHASE  
ALIGNER  
PLL  
PACLK  
PHASE  
DETECTOR  
STOPB  
PCLKM  
2
2
SYNCLKN  
MULT [0:1]  
PWRDWNB  
24-PIN QSOP TOP VIEW  
S0  
V
1
2
3
4
5
6
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
DDR  
S1  
V
REFCLK  
V
DDO  
DDC  
V
V
SS  
SS  
CLK  
N/C  
V
SS  
PCLKM  
SYNCLKN  
CLKB  
7
V
V
SS  
8
SS  
V
DDC  
9
V
DDO  
V
MULT0  
MULT1  
S2  
DDPD  
10  
11  
12  
STOPB  
PWRDWNB  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
October 27, 1998  

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