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CY22050KZXC-XXX PDF预览

CY22050KZXC-XXX

更新时间: 2024-11-23 21:06:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
10页 277K
描述
Clock Generator, 200MHz, CMOS, PDSO16, 4.40 MM, LEAD FREE, MO-153, TSSOP-16

CY22050KZXC-XXX 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:TSSOP包装说明:TSSOP, TSSOP16,.25
针数:16Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.26JESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:5 mm
湿度敏感等级:3端子数量:16
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:200 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:2.5/3.3,3.3 V
主时钟/晶体标称频率:133 MHz认证状态:Not Qualified
座面最大高度:1.1 mm子类别:Clock Generators
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

CY22050KZXC-XXX 数据手册

 浏览型号CY22050KZXC-XXX的Datasheet PDF文件第2页浏览型号CY22050KZXC-XXX的Datasheet PDF文件第3页浏览型号CY22050KZXC-XXX的Datasheet PDF文件第4页浏览型号CY22050KZXC-XXX的Datasheet PDF文件第5页浏览型号CY22050KZXC-XXX的Datasheet PDF文件第6页浏览型号CY22050KZXC-XXX的Datasheet PDF文件第7页 
CY22050,  
CY220501  
One-PLL General Purpose  
Flash Programmable Clock Generator  
Features  
Benefits  
Integrated phase-locked loop (PLL)  
Commercial and Industrial operation  
Flash-programmable  
Internal PLL to generate six outputs up to 200 MHz. Able to  
generate custom frequencies from an external reference  
crystal or driven source.  
Performance guaranteed for applications that require an  
extended temperature range.  
Field-programmable  
Reprogrammabletechnologyallowseasycustomization, quick  
turnaround on design changes and product performance  
enhancements, and better inventory control. Parts can be  
reprogrammed up to 100 times, reducing inventory of custom  
parts and providing an easy method for upgrading existing  
Low-skew, low-jitter, high-accuracy outputs  
3.3V operation with 2.5V output option  
16-Pin TSSOP package (CY22050)  
16-Pin TSSOP package with NiPdAu lead finish (CY220501)  
designs.  
In-house programming of samples and prototype quantities is  
available using the CY3672 FTG Development Kit. Production  
quantities are available through Cypress’s value-added distri-  
bution partners or by using third party programmers from BP  
Microsystems, HiLo Systems, and others.  
Industry standard packaging saves on board space.  
Table 1. Device Selection  
Part Number  
Outputs  
Input Frequency Range  
Output Frequency Range  
Specifications  
CY22050KFZXC  
6
8 MHz–30 MHz (external crystal)  
1 MHz–133 MHz (driven clock)  
80 kHz–200 MHz (3.3V)  
80 KHz–166.6 MHz (2.5V)  
Field-programmable  
commercial temperature  
CY22050KFZXI  
CY220501KFZXI  
6
6
8 MHz–30 MHz (external crystal)  
1 MHz–133 MHz (driven clock)  
80 kHz–166.6 MHz (3.3V)  
80 KHz–150 MHz (2.5V)  
Field-programmable  
industrial temperature  
8 MHz–30 MHz (external crystal)  
1 MHz–133 MHz (driven clock)  
80 kHz–166.6 MHz (3.3V)  
80 KHz–150 MHz (2.5V)  
Field-programmable  
industrial temperature  
NiPdAu lead finish  
Logic Block Diagram  
LCLK1  
LCLK2  
Divider  
Bank 1  
Output  
Select  
Matrix  
LCLK3  
LCLK4  
XIN  
Q
OSC.  
Φ
XOUT  
VCO  
PLL  
P
Divider  
Bank 2  
CLK5  
CLK6  
OE  
AVSS VSS  
VDD  
AVDD  
VDDL VSSL PWRDWN  
Cypress Semiconductor Corporation  
Document #: 38-07006 Rev. *G  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised July 24, 2009  
[+] Feedback  

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