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CP622-2N6027 PDF预览

CP622-2N6027

更新时间: 2024-11-18 14:55:19
品牌 Logo 应用领域
CENTRAL /
页数 文件大小 规格书
4页 470K
描述
40V,150mA Bare die,27.560 X 27.560 mils,Programmable UJT

CP622-2N6027 技术参数

生命周期:Active包装说明:,
Reach Compliance Code:compliant风险等级:5.76
触发设备类型:PROGRAMMABLE UJTBase Number Matches:1

CP622-2N6027 数据手册

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CP622-2N6027  
Programmable  
Unijunction Transistor Die  
www.centralsemi.com  
The CP622-2N6027 is a silicon PUT designed for adjustable characteristics such as Valley  
Current (I ), and Peak Current (I )  
V
P
MECHANICAL SPECIFICATIONS:  
Die Size  
27.5 x 27.5 MILS  
A
Die Thickness  
9.45 MILS  
Anode Bonding Pad Size  
Cathode Bonding Pad Size  
Top Side Metalization  
Back Side Metalization  
Scribe Alley Width  
Wafer Diameter  
7.1 x 5.1 MILS  
7.1 x 5.1 MILS  
Al – 20,000Å  
Au – 13,000Å  
3.6 MILS  
K
3 INCHES  
8,894  
BACKSIDE GATE  
R2  
Gross Die Per Wafer  
MAXIMUM RATINGS: (T =25°C)  
SYMBOL  
UNITS  
V
A
Gate-Cathode Forward Voltage  
Gate-Cathode Reverse Voltage  
Gate-Anode Reverse Voltage  
V
40  
GKF  
GKR  
GAR  
V
V
5.0  
V
V
40  
Anode-Cathode Voltage  
V
40  
5.0  
V
AK  
TSM  
TRM  
TRM  
Peak Non-Repetitive Forward Current (t=10µs)  
Peak Repetitive Forward Current (t=20µs, D.C.=1.0%)  
Peak Repetitive Forward Current (t=100µs, D.C.=1.0%)  
DC Forward Anode Current  
I
A
I
I
2.0  
A
1.0  
A
I
150  
mA  
mA  
°C  
°C  
T
DC Gate Current  
I
50  
G
Operating Junction Temperature  
Storage Temperature  
T
-50 to +100  
-55 to +150  
J
T
stg  
ELECTRICAL CHARACTERISTICS: (T =25°C unless otherwise noted)  
A
SYMBOL  
TEST CONDITIONS  
V =40V  
MIN  
MAX  
10  
UNITS  
nA  
I
I
I
I
I
I
I
GAO  
GKS  
P
S
V =40V  
50  
2.0  
5.0  
50  
nA  
µA  
µA  
µA  
µA  
mA  
V
S
V =10V, R =1.0M  
S
G
V =10V, R =10k  
P
S
G
V =10V, R =1.0M  
V
S
G
V =10V, R =10k  
70  
1.5  
0.2  
0.2  
V
S
G
V =10V, R =200  
V
S
G
V
V
V
V
V =10V, R =1.0M  
1.6  
0.6  
1.5  
T
T
F
O
S
G
V =10V, R =10k  
V
S
G
I =50mA  
V
F
V =20V, C =0.2µF  
6.0  
V
B
C
t
V =20V, C =0.2µF  
80  
ns  
r
B
C
R0 (26-July 2016)  

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