Datasheet > CD82C284-12

CD82C284-12

更新时间： 2024-09-15 22:28:27

品牌	Logo	应用领域
英特矽尔 - INTERSIL		晶体时钟发生器外围集成电路
页数	文件大小	规格书
11页	75K
描述
Clock Generator and Ready Interface for 80C286 Processors

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CD82C284-12 数据手册

82C284

Clock Generator and Ready Interface

for 80C286 Processors

March 1997

Features

Description

• Generates System Clock for 80C286 Processors

The Intersil 82C284 is a clock generator/driver which

provides clock signals for 80C286 processors and support

components. It also contains logic to supply READY to the

CPU from either asynchronous or synchronous sources and

synchronous RESET from an asynchronous input with

hysteresis.

• Generates System Reset Output from Schmitt

Trigger Input

- Improved Hysteresis

• Uses Crystal or External Signal for Frequency Source

• Dynamically Switchable between Two Input

Frequencies

Ordering Information

PKG.

• Provides Local READY and MULTIBUS READY

Synchronization

PART NUMBER

CD82C284-12

ID82C284-10

ID82C284-12

TEMP. RANGE

PACKAGE

18 Ld CERDIP F18.3

-40 C to +85 C 18 Ld CERDIP F18.3

NO.

0 C to +70 C

• Static CMOS Technology

• Single +5V Power Supply

-40 C to +85 C 18 Ld CERDIP F18.3

• Available in 18 Lead CerDIP Package

Pinout

Functional Diagram

82C284 (CERDIP)

TOP VIEW

RESET

ARDY

SRDY

SRDYEN

READY

EFI

18 VCC

17 ARDYEN

16 S1

RES

SYNCHRONIZER

15 S0

XTAL

OSC

14 NC

CLK

MUX

F/C

13 PCLK

12 RESET

11 RES

10 CLK

EFI

F/C

GND

ARDYEN

ARDY

SYNCHRONIZER

READY LOGIC

SRDYEN

SRDY

READY

PCLK

PCLK GENERATOR

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 2966.1

MULTIBUS is a patented Intel bus.

12 3 4 5 6 7...11

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