Datasheet > CD82C50A-5

CD82C50A-5

更新时间： 2024-11-22 22:28:27

品牌	Logo	应用领域
英特矽尔 - INTERSIL		外围集成电路数据传输通信时钟
页数	文件大小	规格书
21页	103K
描述
CMOS Asynchronous Communications Element

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CD82C50A-5 数据手册

82C50A

CMOS Asynchronous

Communications Element

March 1997

Features

Description

• Single Chip UART/BRG

The 82C50A Asynchronous Communication Element (ACE)

is a high performance programmable Universal Asynchro-

nous Receiver/Transmitter (UART) and Baud Rate Genera-

tor (BRG) on a single chip. Using Intersil’s advanced Scaled

SAJI IV CMOS Process, the ACE will support data rates

from DC to 625K baud (0-10MHz clock).

• DC to 625K Baud (DC to 10MHz Clock)

• Crystal or External Clock Input

• On Chip Baud Rate Generator 1 to 65535 Divisor

Generates 16X Clock

• Prioritized Interrupt Mode

• Fully TTL/CMOS Compatible

• Microprocessor Bus Oriented Interface

• 80C86/80C88 Compatible

• Scaled SAJI IV CMOS Process

• Low Power - 1mA/MHz Typical

• Modem Interface

• Line Break Generation and Detection

• Loopback and Echo Modes

• Doubled Buffered Transmitter and Receiver

• Single 5V Supply

The ACE’s receiver circuitry converts start, data, stop, and

parity bits into a parallel data word. The transmitter circuitry

converts a parallel data word into serial form and appends

the start, parity, and stop bits. The word length is program-

mable to 5, 6, 7, or 8 data bits. Stop bit selection provides a

choice of 1,1.5, or 2 stop bits.

The Baud Rate Generator divides the clock by a divisor

programmable from 1 to 2 -1 to provide standard RS-232C

baud rates when using any one of three industry standard

baud rate crystals (1.8432MHz, 2.4576MHz, or 3.072MHz).

A programmable buffered clock output (BAUDOUT) provides

either a buffered oscillator or 16X (16 times the data rate)

baud rate clock for general purpose system use.

Ordering Information

TEMPERATURE

PKG.

PACKAGE

RANGE ( C)

625K BAUD

CP82C50A-5

IP82C50A-5

CS82C50A-5

IS82C50A-5

CD82C50A-5

ID82C50A-5

MD82C50A-5/B

NO.

E40.6

N44.65

F40.6

PDIP

0 to +70

-40 to +85

0 to +70

To meet the system requirements of a CPU interfacing to an

asynchronous channel, the modem control signals RTS,

CTS, DSR, DTR, RI, DCD are provided. Inputs and outputs

have been designed with full TTL/CMOS compatibility in

order to facilitate mixed TTL/NMOS/CMOS system design.

PLCC

-40 to +85

0 to +70

CERDIP

-40 to +85

-55 to +125

Functional Diagram

MICROPROCESSOR INTERFACE

CSO

CS1

CS2

24 CSOUT

DDIS

INTERRUPT

ENABLE,

ID, & CONTROL

30 INTRPT

ADS

UART

SIN

RECEIVER

RCLK

15 BAUDOUT

DISTR 22

DISTR 21

DIVISOR LATCH

AND BAUD RATE

GENERATOR

LINE STATUS

AND CONTROL

XTAL1

XTAL2

DOSTR 19

DOSTR 18

SOUT

RTS

TRANSMITTER

MODEM

DTR

OUT1

MODEM CONTROL

MODEM STATUS

OUT2

CTS

DSR

DCD

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 2958.1

12 3 4 5 6 7...21

中文翻译

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与CD82C50A-5相关器件

型号	品牌	获取价格	描述	数据表
CD82C52	INTERSIL	获取价格	CMOS Serial Controller Interface
CD82C54	INTERSIL	获取价格	CMOS Programmable Interval Timer
CD82C54-10	INTERSIL	获取价格	CMOS Programmable Interval Timer
CD82C54-12	INTERSIL	获取价格	CMOS Programmable Interval Timer
CD82C55A	INTERSIL	获取价格	CMOS Programmable Peripheral Interface
CD82C55A	HARRIS	获取价格	CMOS Programmable Peripheral Interface
CD82C55A-5	HARRIS	获取价格	CMOS Programmable Peripheral Interface
CD82C55A-5	INTERSIL	获取价格	CMOS Programmable Peripheral Interface
CD82C59A	INTERSIL	获取价格	CMOS Priority Interrupt Controller
CD82C59A-12	INTERSIL	获取价格	CMOS Priority Interrupt Controller

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