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CD74HCT40103M96E4 PDF预览

CD74HCT40103M96E4

更新时间： 2024-09-14 23:04:31
品牌 Logo 应用领域
德州仪器 - TI 计数器
页数 文件大小 规格书
14页 280K
描述
High-Speed CMOS Logic 8-Stage Synchronous Down Counters

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CD74HCT40103M96E4 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：GREEN, PLASTIC, MS-012AC, SOIC-16针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.26Is Samacsys：N
其他特性：TCO OUTPUT; RESET TO MAX COUNT计数方向：DOWN
系列：HCTJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：9.9 mm
负载电容（CL）：50 pF负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER最大频率@ Nom-Sup：9000000 Hz
最大I（ol）：0.004 A工作模式：SYNCHRONOUS
湿度敏感等级：1位数：8
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：260电源：5 V
传播延迟（tpd）：90 ns认证状态：Not Qualified
座面最大高度：1.75 mm子类别：Counters
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：3.9 mm最小 fmax：9 MHz
Base Number Matches：1

CD74HCT40103M96E4 数据手册

 浏览型号CD74HCT40103M96E4的Datasheet PDF文件第2页浏览型号CD74HCT40103M96E4的Datasheet PDF文件第3页浏览型号CD74HCT40103M96E4的Datasheet PDF文件第4页浏览型号CD74HCT40103M96E4的Datasheet PDF文件第5页浏览型号CD74HCT40103M96E4的Datasheet PDF文件第6页浏览型号CD74HCT40103M96E4的Datasheet PDF文件第7页 
CD54HC40103, CD74HC40103,  
CD74HCT40103  
Data sheet acquired from Harris Semiconductor  
SCHS221D  
High-Speed CMOS Logic  
8-Stage Synchronous Down Counters  
November 1997 - Revised October 2003  
Features  
Description  
• Synchronous or Asynchronous Preset  
• Cascadable in Synchronous or Ripple Mode  
The ’HC40103 and CD74HCT40103 are manufactured with  
high speed silicon gate technology and consist of an 8-stage  
synchronous down counter with a single output which is  
active when the internal count is zero. The 40103 contains a  
single 8-bit binary counter. Each has control inputs for  
enabling or disabling the clock, for clearing the counter to its  
maximum count, and for presetting the counter either  
[ /Title  
(CD74H  
C40103,  
CD74H  
CT4010  
3)  
/Sub-  
ject  
(High  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C synchronously or asynchronously. All control inputs and the  
TC output are active-low logic.  
• Balanced Propagation Delay and Transition Times  
In normal operation, the counter is decremented by one  
• Significant Power Reduction Compared to LSTTL  
count on each positive transition of the CLOCK (CP).  
Logic ICs  
Counting is inhibited when the TE input is high. The TC  
output goes low when the count reaches zero if the TE input  
is low, and remains low for one full clock period.  
• HC Types  
Speed  
CMOS  
Logic 8-  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
CC  
When the PE input is low, data at the P0-P7 inputs are  
clocked into the counter on the next positive clock transition  
regardless of the state of the TE input. When the PL input is  
low, data at the P0-P7 inputs are asynchronously forced into  
the counter regardless of the state of the PE, TE, or CLOCK  
inputs. Input P0-P7 represent a single 8-bit binary word for  
the 40103. When the MR input is low, the counter is  
IL  
IH  
at V  
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL  
IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
asynchronously cleared to its maximum count of 255  
,
l
10  
regardless of the state of any other input. The precedence  
relationship between control inputs is indicated in the truth  
table.  
Ordering Information  
TEMP. RANGE  
o
If all control inputs except TE are high at the time of zero  
count, the counters will jump to the maximum count, giving a  
PART NUMBER  
CD54HC40103F3A  
CD74HC40103E  
( C)  
PACKAGE  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
counting sequence of 100 or 256 clock pulses long.  
16 10  
The 40103 may be cascaded using the TE input and the TC  
output, in either a synchronous or ripple mode. These  
circuits possess the low power consumption usually  
associated with CMOS circuitry, yet have speeds  
comparable to low power Schottky TTL circuits and can drive  
up to 10 LSTTL loads.  
CD74HC40103M  
CD74HC40103MT  
CD74HC40103M96  
CD74HCT40103E  
CD74HCT40103M  
CD74HCT40103MT  
CD74HCT40103M96  
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel  
of 250.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
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CD74HCT40103M96E4 替代型号

型号 品牌 替代类型 描述 数据表
CD74HCT40103M96G4 TI

完全替代

 High-Speed CMOS Logic 8-Stage Synchronous Down Counters
CD74HCT40103MG4 TI

完全替代

 High-Speed CMOS Logic 8-Stage Synchronous Down Counters
CD74HCT40103M96 TI

完全替代

 High-Speed CMOS Logic 8-Stage Synchronous Down Counters

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 		Parallel In Parallel Out, HCT Series, 4-Bit, Bidirectional, True Output, CMOS, PDSO16

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