Datasheet > 存储 > FIFO> CD74HCT40105E

CD74HCT40105E

更新时间： 2024-11-04 23:04:31

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描述
High Speed CMOS Logic 4-Bit x 16-Word FIFO Register

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CD74HCT40105E 技术参数

是否Rohs认证：	符合	生命周期：	Active
零件包装代码：	DIP	包装说明：	DIP, DIP16,.3
针数：	16	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.71
风险等级：	1.56	最长访问时间：	2250 ns
最大时钟频率 (fCLK)：	10 MHz	周期时间：	100 ns
JESD-30 代码：	R-PDIP-T16	JESD-609代码：	e4
长度：	19.305 mm	内存密度：	64 bit
内存集成电路类型：	OTHER FIFO	内存宽度：	4
功能数量：	1	端子数量：	16
字数：	16 words	字数代码：	16
工作模式：	SYNCHRONOUS	最高工作温度：	125 °C
最低工作温度：	-55 °C	组织：	16X4
输出特性：	3-STATE	可输出：	YES
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP16,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	5.08 mm
子类别：	FIFOs	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	MILITARY	端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm	Base Number Matches：	1

CD74HCT40105E 数据手册

CD74HC40105,

CD74HCT40105

Data sheet acquired from Harris Semiconductor

SCHS222

High Speed CMOS Logic

February 1998

4-Bit x 16-Word FIFO Register

Features

Description

• Independent Asynchronous Inputs and Outputs

• Expandable in Either Direction

• Reset Capability

The Harris CD74HC40105 and CD74HCT40105 are high-

speed silicon-gate CMOS devices that are compatible,

except for “shift-out” circuitry, with the Harris CD40105B.

They are low-power ﬁrst-in-out (FIFO) “elastic” storage

registers that can store 16 four-bit words. The 40105 is

capable of handling input and output data at different shifting

rates. This feature makes particularly useful as a buffer

between asynchronous systems.

[ /Title

(CD74

HC401

05,

CD74

HCT40

105)

/Sub-

ject

(High

Speed

CMOS

• Status Indicators on Inputs and Outputs

• Three-State Outputs

• Shift-Out Independent of Three-State Control

• Fanout (Over Temperature Range)

Each work position in the register is clocked by a control ﬂip-

ﬂop, which stores a marker bit. A “1” signiﬁes that the posi-

tion’s data is ﬁlled and a “0” denotes a vacancy in that posi-

tion. The control ﬂip-ﬂop detects the state of the preceding

ﬂip-ﬂop and communicates its own status to the succeeding

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55 C to 125 C ﬂip-ﬂop. When a control ﬂip-ﬂop is in the “0” state and sees a

“1” in the preceeding ﬂip-ﬂop, it generates a clock pulse that

transfers data from the preceding four data latches into its

• Balanced Propagation Delay and Transition Times

own four data latches and resets the preceding ﬂip-ﬂop to

“0”. The ﬁrst and last control ﬂip-ﬂops have buffered outputs.

Since all empty locations “bubble” automatically to the input

end, and all valid data ripple through to the output end, the

status of the ﬁrst control ﬂip-ﬂop (DATA-IN READY) indicates

if the FIFO is full, and the status of the last ﬂip-ﬂop (DATA-

OUT READY) indicates if the FIFO contains data. As the

earliest data are removed from the bottom of the data stack

(the output end), all data entered later will automatically

propagate (ripple) toward the output.

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N = 30%, N = 30% of V

IL IH CC

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V = 0.8V (Max), V = 2V (Min)

Ordering Information

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

TEMP. RANGE

PART NUMBER

CD74HC40105E

CD74HCT40105E

CD74HC40105M

CD74HCT40105M

NOTES:

( C)

PACKAGE

16 Ld PDIP

16 Ld SOIC

PKG. NO.

E16.3

Applications

-55 to 125

• Bit-Rate Smoothing

• CPU/Terminal Buffering

• Data Communications

• Peripheral Buffering

• Line Printer Input Buffers

• Auto-Dialers

E16.3

M16.15

1. When ordering, use the entire part number. Add the sufﬁx 96 to

obtain the variant in the tape and reel.

2. Wafer and die for this part number is available which meets all

electrical specifications. Please contact your local sales office or

Harris customer service for ordering information.

• CRT Buffer Memories

• Radar Data Acquisition

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

File Number 1834.1

12 3 4 5 6 7...14

中文翻译

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CD74HCT40105E 替代型号

型号	品牌	替代类型	描述	数据表
CD40105BF	TI	完全替代	CMOS FIFO register
CD74HCT40105EE4	TI	完全替代	High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register

与CD74HCT40105E相关器件

型号	品牌	获取价格	描述	数据表
CD74HCT40105EE4	TI	获取价格	High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register
CD74HCT40105H	ETC	获取价格	x4 Asynchronous FIFO
CD74HCT40105M	TI	获取价格	High Speed CMOS Logic 4-Bit x 16-Word FIFO Register
CD74HCT40105M96	TI	获取价格	High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register
CD74HCT40105M96E4	TI	获取价格	High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register
CD74HCT40105M96G4	TI	获取价格	High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register
CD74HCT40105ME4	TI	获取价格	High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register
CD74HCT40105MG4	TI	获取价格	High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register
CD74HCT40105MT	TI	获取价格	High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register
CD74HCT40105MTE4	TI	获取价格	High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register

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