5秒后页面跳转
CD74HCT40105 PDF预览

CD74HCT40105

更新时间: 2024-11-04 23:04:31
品牌 Logo 应用领域
德州仪器 - TI 先进先出芯片
页数 文件大小 规格书
14页 84K
描述
High Speed CMOS Logic 4-Bit x 16-Word FIFO Register

CD74HCT40105 数据手册

 浏览型号CD74HCT40105的Datasheet PDF文件第2页浏览型号CD74HCT40105的Datasheet PDF文件第3页浏览型号CD74HCT40105的Datasheet PDF文件第4页浏览型号CD74HCT40105的Datasheet PDF文件第5页浏览型号CD74HCT40105的Datasheet PDF文件第6页浏览型号CD74HCT40105的Datasheet PDF文件第7页 
CD74HC40105,  
CD74HCT40105  
Data sheet acquired from Harris Semiconductor  
SCHS222  
High Speed CMOS Logic  
February 1998  
4-Bit x 16-Word FIFO Register  
Features  
Description  
• Independent Asynchronous Inputs and Outputs  
• Expandable in Either Direction  
• Reset Capability  
The Harris CD74HC40105 and CD74HCT40105 are high-  
speed silicon-gate CMOS devices that are compatible,  
except for “shift-out” circuitry, with the Harris CD40105B.  
They are low-power first-in-out (FIFO) “elastic” storage  
registers that can store 16 four-bit words. The 40105 is  
capable of handling input and output data at different shifting  
rates. This feature makes particularly useful as a buffer  
between asynchronous systems.  
[ /Title  
(CD74  
HC401  
05,  
CD74  
HCT40  
105)  
/Sub-  
ject  
(High  
Speed  
CMOS  
• Status Indicators on Inputs and Outputs  
• Three-State Outputs  
• Shift-Out Independent of Three-State Control  
• Fanout (Over Temperature Range)  
Each work position in the register is clocked by a control flip-  
flop, which stores a marker bit. A “1” signifies that the posi-  
tion’s data is filled and a “0” denotes a vacancy in that posi-  
tion. The control flip-flop detects the state of the preceding  
flip-flop and communicates its own status to the succeeding  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C flip-flop. When a control flip-flop is in the “0” state and sees a  
“1” in the preceeding flip-flop, it generates a clock pulse that  
transfers data from the preceding four data latches into its  
• Balanced Propagation Delay and Transition Times  
own four data latches and resets the preceding flip-flop to  
“0”. The first and last control flip-flops have buffered outputs.  
Since all empty locations “bubble” automatically to the input  
end, and all valid data ripple through to the output end, the  
status of the first control flip-flop (DATA-IN READY) indicates  
if the FIFO is full, and the status of the last flip-flop (DATA-  
OUT READY) indicates if the FIFO contains data. As the  
earliest data are removed from the bottom of the data stack  
(the output end), all data entered later will automatically  
propagate (ripple) toward the output.  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
Ordering Information  
IL  
IH  
- CMOS Input Compatibility, I 1µA at V , V  
OL OH  
l
TEMP. RANGE  
o
PART NUMBER  
CD74HC40105E  
CD74HCT40105E  
CD74HC40105M  
CD74HCT40105M  
NOTES:  
( C)  
PACKAGE  
16 Ld PDIP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
PKG. NO.  
E16.3  
Applications  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• Bit-Rate Smoothing  
• CPU/Terminal Buffering  
• Data Communications  
• Peripheral Buffering  
• Line Printer Input Buffers  
• Auto-Dialers  
E16.3  
M16.15  
M16.15  
1. When ordering, use the entire part number. Add the suffix 96 to  
obtain the variant in the tape and reel.  
2. Wafer and die for this part number is available which meets all  
electrical specifications. Please contact your local sales office or  
Harris customer service for ordering information.  
• CRT Buffer Memories  
• Radar Data Acquisition  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 1834.1  
Copyright © Harris Corporation 1998  
1

与CD74HCT40105相关器件

型号 品牌 获取价格 描述 数据表
CD74HCT40105E TI

获取价格

High Speed CMOS Logic 4-Bit x 16-Word FIFO Register
CD74HCT40105E ROCHESTER

获取价格

16X4 OTHER FIFO, 100ns, PDIP16
CD74HCT40105EE4 TI

获取价格

High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register
CD74HCT40105H ETC

获取价格

x4 Asynchronous FIFO
CD74HCT40105M TI

获取价格

High Speed CMOS Logic 4-Bit x 16-Word FIFO Register
CD74HCT40105M96 TI

获取价格

High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register
CD74HCT40105M96E4 TI

获取价格

High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register
CD74HCT40105M96G4 TI

获取价格

High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register
CD74HCT40105ME4 TI

获取价格

High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register
CD74HCT40105MG4 TI

获取价格

High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register