CD4070BMS
CD4077BMS
CMOS Quad Exclusive OR and
Exclusive NOR Gates
December 1992
CD4070BMS
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Features
Pinouts
• High Voltage Types (20V Rating)
• CD4070BMS - Quad Exclusive OR Gate
• CD4077BMS - Quad Exclusive NOR Gate
A
B
B
D
C
D
1
2
3
4
5
6
7
14 VDD
13 H
J = A
K = C
12 G
• Medium Speed Operation
11 M = G
10 L = E
H
- tPHL, tPLH = 65ns (Typ.) at VDD = 10V, CL = 50pF
F
• 5V, 10V and 15V Parametric Ratings
9
8
F
E
VSS
• Standardized, Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
CD4077BMS
TOP VIEW
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
A
B
1
2
3
4
5
6
7
14 VDD
13 H
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
J = A
K = C
B
D
C
D
12 G
- 2V at VDD = 10V
11 M = G
10 L = E
H
- 2.5V at VDD = 15V
F
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
9
8
F
E
VSS
Applications
Functional Diagram
• Logical Comparators
• Parity Generators and Checkers
• Adders/Subtractors
1
A
3
J
2
B
J = A
K = C
B
D
5
6
C
D
4
K
L
M = G
L = E
H
F
Description
8
9
E
F
10
11
CD4070BMS contains four independent Exclusive OR gates.
The CD4077BMS contains four independent Exclusive NOR
gates.
VSS = 7
VDD = 14
12
13
G
H
M
The CD4070BMS and CD4077BMS provide the system
designer with a means for direct implementation of the
Exclusive OR and Exclusive NOR functions, respectively.
CD4070BMS
The CD4070BMS and CD4077BMS are supplied in these 14
lead outline packages:
1
2
A
B
3
4
J
Braze Seal DIP
Frit Seal DIP
H4Q
H1B
*H4F
J = A
K = C
B
D
5
6
C
D
K
L
8
9
Ceramic Flatpack
*CD4070B Only
†H3W
E
F
M = G
L = E
H
F
10
11
†CD4077B Only
12
13
G
H
M
CD4077BMS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3322
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