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CD4071BC_02 PDF预览

CD4071BC_02

更新时间: 2024-11-04 04:36:11
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
7页 101K
描述
Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate

CD4071BC_02 数据手册

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October 1987  
Revised April 2002  
CD4071BC CD4081BC  
Quad 2-Input OR Buffered B Series Gate •  
Quad 2-Input AND Buffered B Series Gate  
General Description  
Features  
Low power TTL compatibility:  
The CD4071BC and CD4081BC quad gates are monolithic  
complementary MOS (CMOS) integrated circuits con-  
structed with N- and P-channel enhancement mode tran-  
sistors. They have equal source and sink current  
capabilities and conform to standard B series output drive.  
The devices also have buffered outputs which improve  
transfer characteristics by providing very high gain.  
Fan out of 2 driving 74L or 1 driving 74LS  
5V–10V–15V parametric ratings  
Symmetrical output characteristics  
Maximum input leakage 1 µA at 15V over full  
temperature range  
All inputs protected against static discharge with diodes to  
VDD and VSS.  
Ordering Code:  
Order Number Package Number  
Package Description  
CD4071BCM  
CD4071BCN  
CD4081BCM  
CD4081BCN  
M14A  
N14A  
M14A  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Devices are also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Connection Diagrams  
CD4071B  
CD4081B  
Top View  
Top View  
© 2002 Fairchild Semiconductor Corporation  
DS005977  
www.fairchildsemi.com  

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