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CAT5401YI-10

更新时间： 2024-09-16 04:35:47
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CATALYST 转换器电阻器光电二极管
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描述
Quad Digitally Programmable Potentiometers (DPP⑩) with 64 Taps and SPI Interface

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CAT5401YI-10 数据手册

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CAT5401  
Quad Digitally Programmable Potentiometers  
(DPP™) with 64 Taps and SPI Interface  
FEATURES  
DESCRIPTION  
„ Four linear taper digitally programmable  
The CAT5401 is four Digitally Programmable  
Potentiometers (DPPs™) integrated with control logic  
and 16 bytes of NVRAM memory. Each DPP consists  
of a series of 63 resistive elements connected  
between two externally accessible end points. The tap  
points between each resistive element are connected  
to the wiper outputs with CMOS switches. A separate  
6-bit control register (WCR) independently controls  
the wiper tap switches for each DPP. Associated with  
each wiper control register are four 6-bit non-volatile  
memory data registers (DR) used for storing up to four  
wiper settings. Writing to the wiper control register or  
any of the non-volatile data registers is via a SPI serial  
bus. On power-up, the contents of the first data  
register (DR0) for each of the four potentiometers is  
automatically loaded into its respective wiper control  
register.  
potentiometers  
„ 64 resistor taps per potentiometer  
„ End to end resistance 2.5kΩ, 10kΩ, 50kΩ or  
100kΩ  
„ Potentiometer control and memory access via  
SPI interface: Mode (0, 0) and (1, 1)  
„ Low wiper resistance, typically 80Ω  
„ Nonvolatile memory storage for up to four  
wiper settings for each potentiometer  
„ Automatic recall of saved wiper settings at  
power up  
„ 2.5 to 6.0 volt operation  
„ Standby current less than 1µA  
„ 1,000,000 nonvolatile WRITE cycles  
„ 100 year nonvolatile memory data retention  
„ 24-lead SOIC and 24-lead TSSOP  
„ Industrial temperature range  
The CAT5401 can be used as a potentiometer or as a  
two terminal, variable resistor. It is intended for circuit  
level or system level adjustments in a wide variety of  
applications.  
For Ordering Information details, see page 14.  
PIN CONFIGURATION  
FUNCTIONAL DIAGRAM  
SOIC Package (W)  
TSSOP Package (Y)  
R
H0  
R
H1  
R
R
H3  
H2  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
NC  
R
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
WP  
CS  
R
1
1
V
SI  
CC  
CS  
SCK  
SI  
R
2
A
2
L3  
L0  
1
SPI BUS  
INTERFACE  
ꢀ
WIPER CONTROL  
REGISTERS  
ꢀ
R
W0  
R
W1  
R
W2  
R
W3  
R
H3  
R
3
R
R
3
W0  
H0  
L1  
SO  
R
W3  
R
H0  
R
W0  
CS  
4
4
H1  
A
0
R
L0  
5
R
5
W1  
SO  
V
CC  
NC  
WP  
SI  
6
GND  
6
CAT  
5401  
CAT  
5401  
WP  
NONVOLATILE  
DATA  
REGISTERS  
HOLD  
SCK  
7
NC  
7
A
0
CONTROL LOGIC  
A
1
R
A
1
8
R
8
L3  
W2  
R
L2  
R
H3  
R
9
R
9
L1  
H2  
R
H2  
R
W3  
R
10  
11  
12  
R
10  
11  
12  
H1  
L2  
R
L0  
R
L1  
R
R
L3  
L2  
R
W2  
A
0
SO  
R
W1  
SCK  
NC  
GND  
HOLD  
© Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
1
Doc. No. MD-2012 Rev. G  
1234567...15

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