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CAT5409_08

更新时间： 2024-11-06 04:35:47
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CATALYST /
页数 文件大小 规格书
16页 301K
描述
Quad Digitally Programmable Potentiometers (DPP⑩) with 64 Taps and IC Interface

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CAT5409  
Quad Digitally Programmable Potentiometers  
(DPP™) with 64 Taps and I²C Interface  
FEATURES  
DESCRIPTION  
„ Four linear taper digitally programmable  
The CAT5409 is four Digitally Programmable  
Potentiometers (DPP™) integrated with control logic  
and 16 bytes of NVRAM memory.  
potentiometers  
„ 64 resistor taps per potentiometer  
„ End to end resistance 2.5kΩ, 10kΩ, 50kΩ or  
100kΩ  
A separate 6-bit control register (WCR) independently  
controls the wiper tap position for each DPP.  
Associated with each wiper control register are four  
6-bit non-volatile memory data registers (DR) used for  
storing up to four wiper settings. Writing to the wiper  
control register or any of the non-volatile data  
registers is via a I²C serial bus. On power-up, the  
contents of the first data register (DR0) for each of the  
four potentiometers is automatically loaded into its  
respective wiper control register (WCR).  
„ I²C interface  
„ Low wiper resistance, typically 80Ω  
„ Four non-volatile wiper settings for each  
potentiometer  
„ Recall of saved wiper settings at power-up  
„ 2.5 to 6.0 volt operation  
„ Standby current less than 1µA  
„ 1,000,000 nonvolatile WRITE cycles  
„ 100 year nonvolatile memory data retention  
„ 24-lead SOIC and 24-lead TSSOP  
„ Write protection for data register  
¯¯¯  
The Write Protection (WP) pin protects against  
inadvertent programming of the data register.  
The CAT5409 can be used as a potentiometer or as a  
two terminal, variable resistor. It is intended for circuit  
level or system level adjustments in a wide variety of  
applications.  
For Ordering Information details, see page 15.  
FUNCTIONAL DIAGRAM  
PIN CONFIGURATION  
R
R
R
H2  
R
H3  
H0  
H1  
SOIC (W)  
TSSOP (Y)  
V
1
2
24  
23  
22  
21  
20  
1
2
24 NC  
SCL  
SDA  
SDA  
WP  
CC  
I²C BUS  
INTERFACE  
WIPER CONTROL  
REGISTERS  
R
R
R
R
W0  
W1  
W2  
W3  
A
2
R
R
R
R
A
23  
A
L0  
L3  
1
WP  
R
R
R
3
3
22  
21  
20  
19  
18  
R
R
W0  
H0  
H3  
W3  
L1  
R
R
V
4
4
W0  
A
0
H0  
L0  
H1  
NONVOLATILE  
DATA  
REGISTERS  
A
A
A
1
2
3
CONTROL LOGIC  
A
2
5
5
R
0
W1  
6
19  
18  
17  
16  
15  
14  
13  
6
NC  
GND  
NC  
WP  
CC  
NC  
SDA  
A
3
7
7
R
R
R
L2  
R
L3  
L0  
L1  
A
1
17 SCL  
8
8
R
R
R
R
W2  
L3  
R
9
R
R
9
16  
15  
14  
13  
R
R
R
H2  
H3  
W3  
L1  
L2  
R
10  
11  
12  
10  
11  
12  
H1  
H2  
W2  
L2  
R
SCL  
A
W1  
0
A
3
NC  
GND  
NC  
© Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
1
Doc. No. MD-2010 Rev. K  
1234567...16

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