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CAT5409BI-25-TE13

更新时间： 2024-11-30 21:55:19
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17页 97K
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Quad Digitally Programmable Potentiometers (DPPTM) with 64 Taps and 2-wire Interface

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CAT5409BI-25-TE13 数据手册

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E
CAT5409  
Quad Digitally Programmable Potentiometers (DPP™) with 64 Taps and  
2-wire Interface  
TM  
FEATURES  
■ Recall of saved wiper settings at power-up  
■ 2.5 to 6.0 volt operation  
■ Four linear-taper digital potentiometers  
■ 64 resistor taps per potentiometer  
■ End-to-end resistance 2.5kΩ, 10kΩ, 50kΩ or 100kΩ  
■ 2-wire interface (I2C like)  
■ Standby current less than 1µA  
■ 1,000,000 nonvolatile WRITE cycles  
■ 100 year nonvolatile memory data retention  
■ 24-lead SOIC, 24-lead TSSOP and BGA  
■ Write protection for data register  
■ Low wiper resistance, typically 80Ω  
■ Four non-volatile wiper settings for each  
potentiometer  
DESCRIPTION  
The CAT5409 is four Digitally Programmable  
Potentiometers (DPP™) integrated with control logic  
and 16 bytes of NVRAM memory.  
contents of the first data register (DR0) for each of the  
four potentiometers is automatically loaded into its  
respective wiper control register (WCR).  
A separate 6-bit control register (WCR) independently  
controls the wiper tap position for each DPP.  
Associated with each wiper control register are four 6-  
bit non-volatile memory data registers (DR) used for  
storing up to four wiper settings. Writing to the wiper  
control register or any of the non-volatile data registers  
is via a 2-wire serial bus (I2C-like). On power-up, the  
The Write Protection (WP) pin protects against  
inadvertent programming of the data register.  
The CAT5409 can be used as a potentiometer or as  
a two terminal, variable resistor. It is intended for  
circuit level or system level adjustments in a wide  
variety of applications.  
FUNCTIONAL DIAGRAM  
PIN CONFIGURATION  
SOIC Package (J, W)  
TSSOP Package (U, Y)  
R
R
H3  
R
R
H2  
H1  
H0  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
NC  
R
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
WP  
V
1
SDA  
1
CC  
A
2
R
2
A
1
2
L3  
L0  
R
R
A
R
W0  
R
3
R
L1  
3
R
R
R
H3  
H0  
W0  
W1  
W2  
W3  
WIPER  
CONTROL  
REGISTERS  
SCL  
SDA  
2-WIRE BUS  
INTERFACE  
R
R
V
R
W0  
4
R
H1  
4
W3  
H0  
A
2
5
R
W1  
5
0
L0  
NC  
WP  
6
GND  
NC  
6
CC  
WP  
CAT  
5409  
CAT  
5409  
A
3
NC  
SDA  
7
7
A0  
A1  
A2  
A3  
NONVOLATILE  
DATA  
REGISTERS  
SCL  
R
R
R
A
A
1
8
R
8
CONTROL  
LOGIC  
L3  
W2  
R
L2  
R
9
R
H2  
9
H3  
W3  
R
L1  
R
H2  
R
10  
11  
12  
R
L2  
10  
11  
12  
H1  
R
W2  
R
W1  
SCL  
0
R
R
L3  
R
R
L2  
L0  
L1  
NC  
NC  
GND  
A
3
1
2
3
4
R
W0  
A
A
R
L1  
2
1
A
R
WP  
SDA  
R
W1  
L0  
B
C
D
E
F
V
R
R
V
CC  
H0  
H3  
H1  
H2  
SS  
NC  
BGA  
NC  
R
R
R
L3  
NC  
A
3
R
W2  
R
W3  
A
SCL  
R
L2  
0
Top View - Bump Side Down  
1
© 2004 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Document No. 2010, Rev. I  
1234567...17

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