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CAT5409B-25-TE13 PDF预览

CAT5409B-25-TE13

更新时间: 2024-11-07 09:33:23
品牌 Logo 应用领域
CATALYST 转换器电阻器
页数 文件大小 规格书
17页 106K
描述
QUAD 2.5K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PBGA24, BGA-24

CAT5409B-25-TE13 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:BGA包装说明:VFBGA, BGA24,4X6,20
针数:24Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.1其他特性:NONVOLATILE MEMORY
控制接口:2-WIRE SERIAL转换器类型:DIGITAL POTENTIOMETER
JESD-30 代码:R-PBGA-B24JESD-609代码:e0
功能数量:4位置数:64
端子数量:24最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:VFBGA封装等效代码:BGA24,4X6,20
封装形状:RECTANGULAR封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):240电源:3/5 V
认证状态:Not Qualified电阻定律:LINEAR
最大电阻容差:20%最大电阻器端电压:5 V
最小电阻器端电压:座面最大高度:0.765 mm
子类别:Digital Potentiometers标称供电电压:5 V
表面贴装:YES技术:CMOS
标称温度系数:300 ppm/ °C温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:BALL
端子节距:0.5 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30标称总电阻:2500 Ω
Base Number Matches:1

CAT5409B-25-TE13 数据手册

 浏览型号CAT5409B-25-TE13的Datasheet PDF文件第2页浏览型号CAT5409B-25-TE13的Datasheet PDF文件第3页浏览型号CAT5409B-25-TE13的Datasheet PDF文件第4页浏览型号CAT5409B-25-TE13的Datasheet PDF文件第5页浏览型号CAT5409B-25-TE13的Datasheet PDF文件第6页浏览型号CAT5409B-25-TE13的Datasheet PDF文件第7页 
Preliminary Information  
E
CAT5409  
Quad Digitally Programmable Potentiometers (DPP™) with 64 Taps and  
2-wire Interface  
TM  
FEATURES  
Recall of saved wiper settings at power-up  
2.5 to 6.0 volt operation  
Four linear-taper digital potentiometers  
64 resistor taps per potentiometer  
End-to-end resistance 2.5k, 10k, 50kor 100kΩ  
2-wire interface (I2C like)  
Standby current less than 1µA  
1,000,000 nonvolatile WRITE cycles  
100 year nonvolatile memory data retention  
24-lead SOIC, 24-lead TSSOP and BGA  
Write protection for data register  
Low wiper resistance, typically 80  
Four non-volatile wiper settings for each  
potentiometer  
DESCRIPTION  
four potentiometers is automatically loaded into its  
respective wiper control register (WCR).  
The CAT5409 is four Digitally Programmable  
Potentiometers (DPP™) integrated with control logic  
and 16 bytes of NVRAM memory.  
The Write Protection (WP) pin protects against  
inadvertent programming of the data register.  
A separate 6-bit control register (WCR) independently  
controls the wiper tap position for each DPP.  
Associated with each wiper control register are four 6-  
bit non-volatile memory data registers (DR) used for  
storing up to four wiper settings. Writing to the wiper  
control register or any of the non-volatile data registers  
is via a 2-wire serial bus (I2C-like). On power-up, the  
contents of the first data register (DR0) for each of the  
The CAT5409 can be used as a potentiometer or as  
a two terminal, variable resistor. It is intended for  
circuit level or system level adjustments in a wide  
variety of applications. Available in 0°C to 70°C and  
-40°C to 85°C operating temperature ranges, the  
CAT5409 is offered in 24-lead SOIC and TSSOP  
packages or in a chip scale BGA.  
FUNCTIONAL DIAGRAM  
PIN CONFIGURATION  
SOIC Package (J, W)  
TSSOP Package (U, Y)  
R
R
H3  
R
R
H2  
H1  
H0  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
NC  
R
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
WP  
V
1
SDA  
1
CC  
A
2
R
2
A
1
2
L3  
L0  
R
R
A
R
W0  
R
R
3
R
L1  
3
R
R
R
H3  
H0  
W0  
W1  
W2  
W3  
WIPER  
CONTROL  
REGISTERS  
SCL  
SDA  
2-WIRE BUS  
INTERFACE  
R
R
V
4
R
H1  
4
W3  
H0  
L0  
W0  
A
2
5
R
W1  
5
0
NC  
WP  
6
GND  
NC  
6
CC  
WP  
CAT  
5409  
CAT  
5409  
A
3
NC  
SDA  
7
7
A0  
A1  
A2  
A3  
NONVOLATILE  
DATA  
REGISTERS  
SCL  
R
R
R
A
A
1
8
R
8
CONTROL  
LOGIC  
L3  
W2  
R
L2  
R
9
R
H2  
9
H3  
W3  
R
L1  
R
H2  
R
10  
11  
12  
R
L2  
10  
11  
12  
H1  
R
W2  
R
W1  
SCL  
0
R
R
L3  
R
R
L2  
L0  
L1  
NC  
NC  
GND  
A
3
1
2
3
4
R
W0  
A
2
A
1
R
L1  
A
R
WP  
SDA  
R
W1  
L0  
B
C
D
E
F
V
CC  
R
R
V
H0  
H3  
H1  
H2  
SS  
NC  
BGA  
NC  
R
R
R
L3  
NC  
A
R
W2  
3
R
W3  
A
0
SCL  
R
L2  
Top View - Bump Side Down  
1
© 2003 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Document No. 2010, Rev. H  

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