Datasheet > BUK9K52-60E

BUK9K52-60E

更新时间： 2024-11-24 11:13:11

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
13页	735K
描述
Dual N-channel 60 V, 55 mΩ logic level MOSFETProduction

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BUK9K52-60E 数据手册

BUK9K52-60E

Dual N-channel 60 V, 55 mΩ logic level MOSFET

24 February 2015

Product data sheet

1. General description

Dual logic level N-channel MOSFET in an LFPAK56D (Dual Power-SO8) package using

TrenchMOS technology. This product has been designed and qualified to AEC Q101

standard for use in high performance automotive applications.

2. Features and benefits

Dual MOSFET

Q101 Compliant

•

Repetitive avalanche rated

Suitable for thermally demanding environments due to 175 °C rating

True logic level gate with V_GS(th)rating of greater than 0.5 V at 175 °C

3. Applications

12 V Automotive systems

Motors, lamps and solenoid control

Transmission control

•

Ultra high performance power switching

4. Quick reference data

Table 1.

Symbol

Quick reference data

Parameter

Conditions

Min

Typ

Max

Unit

V_DS

I_D

drain-source voltage

drain current

T_j≥ 25 °C; T_j≤ 175 °C

V_GS= 5 V; T_mb= 25 °C; Fig. 2

P_tot

total power dissipation T_mb= 25 °C; Fig. 1

Static characteristics FET1 and FET2

R_DSon

drain-source on-state

resistance

V_GS= 5 V; I_D= 5 A; T_j= 25 °C; Fig. 12

47.3

2.3

mΩ

Dynamic characteristics FET1 and FET2

Q_GDgate-drain charge

I_D= 5 A; V_DS= 48 V; V_GS= 5 V;

T_j= 25 °C; Fig. 14; Fig. 15

12 3 4 5 6 7...13

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