Datasheet > BUK9515

BUK9515

更新时间： 2024-09-30 22:32:31

品牌	Logo	应用领域
恩智浦 - NXP		晶体晶体管
页数	文件大小	规格书
8页	66K
描述
TrenchMOS transistor Logic level FET

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中文翻译

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BUK9515 数据手册

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

BUK9515-100A

GENERAL DESCRIPTION

QUICK REFERENCE DATA

N-channel enhancement mode logic

level field-effect power transistor in a

plastic envelope using ’trench’

technology which features very low

on-state resistance. It is intended for

use in automotive and general

purpose switching applications.

SYMBOL

PARAMETER

MAX.

UNIT

V_DS

I_D

P_tot

T_j

Drain-source voltage

Drain current (DC)

Total power dissipation

Junction temperature

Drain-source on-state

100

230

175

˚C

R_DS(ON)

resistance

V_GS= 5 V

V_GS= 10 V

14.4

mΩ

PINNING - TO220AB

PIN CONFIGURATION

SYMBOL

DESCRIPTION

tab

gate

drain

source

tab drain

1 2 3

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_DS

Drain-source voltage

Drain-gate voltage

Gate-source voltage

Non-repetitive gate-source voltage t_p≤50µS

100

V_DGR

±V_GS

±V_GSM

R_GS= 20 kΩ

I_D

I_DM

P_tot

T_stg, T_j

Drain current (DC)

Drain current (pulse peak value)

Total power dissipation

Storage & operating temperature

T_mb= 25 ˚C

240

230

175

˚C

T_mb= 100 ˚C

T_mb= 25 ˚C

- 55

THERMAL RESISTANCES

SYMBOL PARAMETER

CONDITIONS

TYP.

MAX.

UNIT

R_{th j-mb}

R_{th j-a}

Thermal resistance junction to

mounting base

Thermal resistance junction to

ambient

0.65

K/W

in free air

K/W

December 1998

Rev 1.100

12 3 4 5 6 7 8

中文翻译

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