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BU9832GUL-WE2 PDF预览

BU9832GUL-WE2

更新时间: 2024-10-28 09:02:19
品牌 Logo 应用领域
罗姆 - ROHM 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
19页 504K
描述
WL-CSP EEPROM family SPI BUS

BU9832GUL-WE2 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:BGA
包装说明:ROHS COMPLIANT, VCSP-8针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.51Factory Lead Time:11 weeks
风险等级:5.75最大时钟频率 (fCLK):5 MHz
数据保留时间-最小值:40耐久性:1000000 Write/Erase Cycles
JESD-30 代码:R-PBGA-B8长度:2.09 mm
内存密度:8192 bit内存集成电路类型:EEPROM
内存宽度:8功能数量:1
端子数量:8字数:1024 words
字数代码:1000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:1KX8封装主体材料:PLASTIC/EPOXY
封装代码:VFBGA封装等效代码:BGA8,3X3,20
封装形状:RECTANGULAR封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行:SERIAL峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/5 V认证状态:Not Qualified
座面最大高度:0.55 mm串行总线类型:SPI
最大待机电流:0.000002 A子类别:EEPROMs
最大压摆率:0.003 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.8 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:0.5 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:1.85 mm
最长写入周期时间 (tWC):5 ms写保护:HARDWARE
Base Number Matches:1

BU9832GUL-WE2 数据手册

 浏览型号BU9832GUL-WE2的Datasheet PDF文件第7页浏览型号BU9832GUL-WE2的Datasheet PDF文件第8页浏览型号BU9832GUL-WE2的Datasheet PDF文件第9页浏览型号BU9832GUL-WE2的Datasheet PDF文件第11页浏览型号BU9832GUL-WE2的Datasheet PDF文件第12页浏览型号BU9832GUL-WE2的Datasheet PDF文件第13页 
Technical Note  
BU9832GUL-W  
4. Status register write / read command  
CS  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
SCK  
SI  
bit7  
WPEN  
bit6  
bit5  
bi t4  
bit3  
bit2  
bit1  
bit0  
BP1 BP0  
0
0
0
0
0
0
0
1
High-Z  
SO  
=Don't care  
Fig.39 Status register write command  
Write status register command can write status register data. The data can be written by this command are 2 bits* 1, that is,  
BP1 (bit3) and BP0 (bit2) among 8 bits of status register. By BP1 and BP0, write disable block of EEPROM can be set. As  
for this command, set CS LOW, and input ope code of write status register, and input data. Then, by making CS HIGH,  
EEPROM starts writing. Write time requires time of tE/W as same as write. As for CS rise, start CS after taking the last  
data bit (bit0), and before the next SCK clock starts. At other timing, command is cancelled. Write disable block is  
determined by BP1 and BP0, and the block can be selected from 1/4 of memory array, 1/2, and entire memory array.  
(Refer to the write disable block setting table.) To the write disabled block, write cannot be made, and only read can be  
made.  
*1 3bits including 1WPEN (bit7)  
CS  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
SCK  
SI  
0
0
0
0
1
0
1
0
bit7  
WPEN  
bit6  
bit5  
bit4  
bit3  
bit2  
bit1  
WEN  
bit0  
R/B  
High-Z  
0
0
0
BP1 BP0  
SO  
Fig.40 Status register read command  
www.rohm.com  
© 2010 ROHM Co., Ltd. All rights reserved.  
2010.10 - Rev.A  
10/18  

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