Datasheet > BU91797MUF-ME2

BU91797MUF-ME2

更新时间： 2024-01-12 03:30:33

品牌	Logo	应用领域
罗姆 - ROHM		驱动接口集成电路
页数	文件大小	规格书
27页	2367K
描述
Low Duty LCD Segment Driver for Automotive application

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中文翻译

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技术参数
数据手册

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BU91797MUF-ME2 技术参数

是否Rohs认证：	符合	生命周期：	Active
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	Factory Lead Time：	13 weeks
风险等级：	2.25	接口集成电路类型：	LIQUID CRYSTAL DISPLAY DRIVER
峰值回流温度（摄氏度）：	NOT SPECIFIED	处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

BU91797MUF-ME2 数据手册

Datasheet

BU91797MUF-M

MAX 144 segments (SEG36×COM4)

Command Transfer Method

Issue Slave Address (“01111100”) after generating “START condition”.

The 1^stbyte after Slave Address always becomes command input.

MSB (“command or data judge bit”) of command decide to next data is command or display data.

When set “command or data judge bit”=‘1’, next byte will be command.

When set “command or data judge bit”=‘0’, next byte data is display data.

Slave address

Display Data

Command

A 1

…

Command

It cannot accept input command once it enters into display data transfer state.

In order to input command again it is necessary to generate “START condition”.

If “START condition” or “STOP condition” is sent in the middle of command transmission, command will be cancelled.

If Slave address is continuously sent following “START condition”, it remains in command input state.

“Slave address” must be sent right after the “START condition”.

When Slave Address cannot be recognized in the first data transmission, no Acknowledge bit is generated and next

transmission will be invalid. When data is invalid status, if “START condition” is transmitted again, it will return to valid

status.

Consider the MPU interface characteristic such as Input rise time and Setup/Hold time when transferring command and

data (Refer to MPU Interface).

Write Display and Transfer Method

BU91797MUF-M has Display Data RAM (DDRAM) of 36×4=144bit.

The relationship between data input and display data, DDRAM data and address are as follows;

Slave address

01111100

Command

0 0000000

A … P

Display Data

8-bit data is stored in DDRAM. ADSET command specifies the address to be written, and address is automatically

incremented in every 4-bit data.

Data can be continuously written in DDRAM by transmitting data continuously.

When RAM data is written successively, after writing RAM data to 23h (SEG35), the address is returned to 00h (SEG0) by

the auto-increment function

DDRAM address

・・・

21h

22h

23h

COM0

COM1

COM2

COM3

BIT

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG33 SEG34 SEG35

Display data is written to DDRAM every 4-bit data.

No need to wait for ACK bit to complete data transfer.

www.rohm.com

TSZ02201-0P4P0D301040-1-2

21.Dec.2015 Rev.001

8/23

TSZ22111･15･001

1...5 6 789 10 11...27

中文翻译

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