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BS616LV2012DC PDF预览

BS616LV2012DC

更新时间: 2024-11-30 23:04:27
品牌 Logo 应用领域
BSI 静态存储器
页数 文件大小 规格书
10页 218K
描述
Very Low Power/Voltage CMOS SRAM 128K X 16 bit

BS616LV2012DC 数据手册

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Very Low Power/Voltage CMOS SRAM  
128K X 16 bit  
BSI  
BS616LV2012  
„ FEATURES  
„ DESCRIPTION  
• Very low operation voltage : 2.7 ~ 3.6V  
• Very low power consumption :  
The BS616LV2012 is a high performance, very low power CMOS Static  
Random Access Memory organized as 131,072 words by 16 bits and  
operates from a wide range of 2.7V to 3.6V supply voltage.  
Advanced CMOS technology and circuit techniques provide both high  
speed and low power features with a typical CMOS standby current  
of 0.15uA and maximum access time of 70/100ns in 3V operation.  
Easy memory expansion is provided by active LOW chip  
enable(CE), active LOW output enable(OE) and three-state output  
drivers.  
Vcc = 3.0V  
C-grade: 30mA (Max.) operating current  
I -grade: 35mA (Max.) operating current  
0.15uA (Typ.) CMOS standby current  
• High speed access time :  
-70  
-10  
70ns (Max.) at Vcc = 3.0V  
100ns (Max.) at Vcc = 3.0V  
•Automatic power down when chip is deselected  
• Three state outputs and TTL compatible  
• Fully static operation  
The BS616LV2012 has an automatic power down feature, reducing the  
power consumption significantly when chip is deselected.  
The BS616LV2012 is available in DICE form, JEDEC standard  
48-pin TSOP Type I package and 48-pin BGA type.  
• Data retention supply voltage as low as 1.5V  
• Easy expansion with CE and OE options  
• I/O Configuration x8/x16 selectable by LB and UB pin  
„ PRODUCT FAMILY  
POWER DISSIPATION  
SPEED  
(ns)  
STANDBY  
Operating  
PRODUCT  
FAMILY  
OPERATING  
Vcc  
( ICCSB1, Max )  
( ICC, Max )  
PKG TYPE  
DICE  
TSOP1-48  
BGA-48-0608  
DICE  
TEMPERATURE  
RANGE  
Vcc=3.0V  
Vcc=3.0V  
8uA  
Vcc=3.0V  
30mA  
BS616LV2012DC  
BS616LV2012TC  
BS616LV2012AC  
BS616LV2012DI  
BS616LV2012TI  
+0 O C to +70 O  
-40 O C to +85 O  
C
C
2.7V ~ 3.6V  
2.7V ~ 3.6V  
70 / 100  
TSOP1-48  
70 / 100  
12uA  
35mA  
BS616LV2012AI  
BGA-48-0608  
„ PIN CONFIGURATIONS  
„ BLOCK DIAGRAM  
A8  
A13  
A15  
A16  
A14  
Address  
1
2
3
4
5
6
20  
1024  
Input  
Row  
Decoder  
Memory Array  
1024 x 2048  
A12  
A7  
A6  
A5  
A4  
A
B
C
D
E
F
LB  
D8  
D9  
OE  
UB  
A0  
A3  
A1  
A4  
A2  
N.C.  
D0  
Buffer  
CE  
D1  
2048  
D10  
A5  
A6  
D2  
Data  
16  
16  
16  
Column I/O  
Input  
DQ0  
VSS  
VCC  
D11  
D12  
N.C.  
N.C.  
A14  
A7  
D3  
VCC  
VSS  
Buffer  
.
.
.
.
.
.
.
.
Write Driver  
Sense Amp  
A16  
A15  
A13  
A10  
D4  
128  
Data  
16  
Output  
D14  
D13  
D5  
D6  
D7  
Buffer  
Column Decoder  
DQ15  
N.C.  
A8  
G
H
D15  
N.C.  
A12  
A9  
WE  
A11  
14  
CE  
WE  
OE  
UB  
N.C.  
Control  
Address Input Buffer  
LB  
A11 A9 A3 A2 A1  
A0 A10  
Vcc  
Gnd  
48-ball BGA top view  
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.  
Revision 2.4  
April 2002  
R0201-BS616LV2012  
1

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