Very Low Power/Voltage CMOS SRAM
128K X 16 bit
BSI
BS616LV2015
DESCRIPTION
FEATURES
The BS616LV2015 is a high performance, very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a wide range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.6uA and maximum access time of 70/55ns in 5V operation.
Easy memory expansion is provided by an active LOW chip
enable(CE), active LOW output enable(OE) and three-state output
drivers.
• Very low operation voltage : 4.5 ~ 5.5V
• Very low power consumption :
Vcc = 5.0V
C-grade: 40mA (Max.) operating current
I -grade: 45mA (Max.) operating current
0.6uA (Typ.) CMOS standby current
• High speed access time :
-70
-55
70ns (Max.) at Vcc = 5.0V
55ns (Max.) at Vcc = 5.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
The BS616LV2015 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV2015 is available in DICE form, JEDEC standard 44-pin
TSOP Type II package, JEDEC standard 44-pin TSOP Type II package
and 48-pin BGA package.
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
PRODUCT FAMILY
POWER DISSIPATION
SPEED
(ns)
STANDBY
Operating
PRODUCT
FAMILY
OPERATING
Vcc
(ICCSB1, Max)
(ICC, Max)
PKG TYPE
DICE
TEMPERATURE
RANGE
Vcc=5.0V
Vcc=5.0V
Vcc=5.0V
BS616LV2015DC
BS616LV2015EC
BS616LV2015TC
BS616LV2015AC
BS616LV2015DI
BS616LV2015EI
BS616LV2015TI
BS616LV2015AI
TSOP2-44
TSOP1-48
BGA-48-0608
DICE
+0 O C to +70O
-40 O C to +85O
C
C
4.5V ~ 5.5V
4.5V ~ 5.5V
70 / 55
6uA
40mA
TSOP2-44
TSOP1-48
BGA-48-0608
70 / 55
10uA
45mA
PIN CONFIGURATIONS
BLOCK DIAGRAM
1
44
A4
A5
2
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A3
A6
3
A2
A7
4
A1
OE
5
A8
A13
A0
UB
6
CE
LB
7
DQ0
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A15
A16
A14
A12
A7
8
DQ1
Address
9
DQ2
20
1024
BS616LV2015EC
10
DQ3
Input
11
Row
VCC
Memory Array
1024 x 2048
BS616LV2015EI
12
GND
13
Buffer
DQ4
14
Decoder
DQ5
15
DQ6
A6
A5
A4
16
DQ7
17
WE
18
A16
A8
A9
A10
A11
NC
19
2048
Column I/O
A15
20
A14
Data
21
A13
16
16
16
Input
22
A12
DQ0
Buffer
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
1
2
3
4
5
6
128
A
B
C
D
E
F
LB
D8
D9
OE
UB
A0
A3
A1
A4
A2
N.C.
D0
Data
16
Output
Buffer
Column Decoder
DQ15
CE
D1
D10
D11
D12
D13
A5
A6
D2
14
CE
WE
OE
UB
VSS
VCC
N.C.
N.C.
A14
A12
A9
A7
D3
D4
VCC
VSS
D6
Control
Address Input Buffer
A16
A15
A13
A10
LB
A11 A9 A3 A2 A1
A0 A10
D14
D15
N.C.
D5
Vcc
Gnd
G
H
WE
A11
D7
N.C.
A8
N.C.
48-ball BGA top view
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
Revision 2.5
April 2002
R0201-BS616LV2015
1