Very Low Power/Voltage CMOS SRAM
128K X 16 bit
BSI
BS616LV2013
FEATURES
DESCRIPTION
• Very low operation voltage : 2.4 ~ 3.6V
• Very low power consumption :
The BS616LV2013 is a high performance, very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a wide range of 2.4V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.1uA and maximum access time of 70/100ns in 3V operation.
Easy memory expansion is provided by active LOW chip
enable(CE), active LOW output enable(OE) and three-state output
drivers.
Vcc = 3.0V
C-grade: 20mA (Max.) operating current
I -grade: 25mA (Max.) operating current
0.1uA (Typ.) CMOS standby current
• High speed access time :
-70
-10
70ns (Max.) at Vcc = 3.0V
100ns (Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
The BS616LV2013 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV2013 is available in DICE form, JEDEC standard 44-pin
TSOP Type II package , JEDEC standard 48-pin TSOP Type I package
and 48-ball BGA package.
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
PRODUCT FAMILY
POWER DISSIPATION
SPEED
( ns )
(SICTCASBN1,DMBaxY)
Operating
PRODUCT
FAMILY
OPERATING
Vcc
( ICC, Max )
PKG TYPE
TEMPERATURE
RANGE
Vcc=3.0V
Vcc=3.0V
Vcc=3.0V
BS616LV2013DC
BS616LV2013EC
BS616LV2013TC
BS616LV2013AC
BS616LV2013DI
BS616LV2013EI
BS616LV2013TI
BS616LV2013AI
DICE
TSOP2-44
TSOP1-48
BGA-48-0608
DICE
+0 O C to +70O
-40 O C to +85O
C
C
2.4V ~3.6V
2.4V ~ 3.6V
70/100
0.7uA
1.5uA
20mA
TSOP2-44
TSOP1-48
BGA-48-0608
70/100
25mA
PIN CONFIGURATIONS
BLOCK DIAGRAM
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A5
2
A3
A6
3
A2
A7
4
A1
A8
A13
OE
5
A0
UB
6
CE
LB
7
A15
A16
A14
DQ0
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
Address
8
DQ1
20
1024
9
DQ2
Input
10
DQ3
Row
BS616LV2013EC
Memory Array
1024 x 2048
11
VCC
A12
A7
12
BS616LV2013EI
GND
Buffer
13
DQ4
Decoder
14
DQ5
A6
A5
A4
15
DQ6
16
DQ7
17
WE
18
A16
A8
A9
A10
A11
NC
2048
19
A15
Data
20
A14
16
16
16
21
Column I/O
Input
A13
DQ0
22
A12
Buffer
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
1
2
3
4
5
6
128
Data
16
Output
A
B
C
D
E
F
LB
D8
D9
OE
UB
A0
A3
A1
A4
A2
N.C.
D0
Buffer
Column Decoder
DQ15
CE
D1
14
CE
WE
OE
UB
D10
D11
D12
D13
A5
A6
D2
Control
Address Input Buffer
VSS
VCC
N.C.
N.C.
A14
A12
A9
A7
D3
VCC
VSS
LB
A11 A9 A3 A2 A1
A0 A10
A16
A15
A13
A10
D4
Vcc
Gnd
D14
D15
N.C.
D5
D6
G
H
WE
A11
D7
N.C.
A8
N.C.
Brillia4n8-cbaell BSGeAmtopivcieow nductor Inc. reserves the right to modify document contents without notice.
Revision 2.5
April 2002
R0201-BS616LV2013
1