Datasheet > BS616LV2012TC

BS616LV2012TC

更新时间： 2022-12-14 13:33:10

品牌	Logo	应用领域
BSI		静态存储器
页数	文件大小	规格书
10页	218K
描述
Very Low Power/Voltage CMOS SRAM 128K X 16 bit

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数据手册

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BS616LV2012TC 数据手册

Very Low Power/Voltage CMOS SRAM

128K X 16 bit

BSI

BS616LV2012

FEATURES

DESCRIPTION

• Very low operation voltage : 2.7 ~ 3.6V

• Very low power consumption :

The BS616LV2012 is a high performance, very low power CMOS Static

Random Access Memory organized as 131,072 words by 16 bits and

operates from a wide range of 2.7V to 3.6V supply voltage.

Advanced CMOS technology and circuit techniques provide both high

speed and low power features with a typical CMOS standby current

of 0.15uA and maximum access time of 70/100ns in 3V operation.

Easy memory expansion is provided by active LOW chip

enable(CE), active LOW output enable(OE) and three-state output

drivers.

Vcc = 3.0V

C-grade: 30mA (Max.) operating current

I -grade: 35mA (Max.) operating current

0.15uA (Typ.) CMOS standby current

• High speed access time :

-70

-10

70ns (Max.) at Vcc = 3.0V

100ns (Max.) at Vcc = 3.0V

•Automatic power down when chip is deselected

• Three state outputs and TTL compatible

• Fully static operation

The BS616LV2012 has an automatic power down feature, reducing the

power consumption significantly when chip is deselected.

The BS616LV2012 is available in DICE form, JEDEC standard

48-pin TSOP Type I package and 48-pin BGA type.

• Data retention supply voltage as low as 1.5V

• Easy expansion with CE and OE options

• I/O Configuration x8/x16 selectable by LB and UB pin

PRODUCT FAMILY

POWER DISSIPATION

SPEED

(ns)

STANDBY

Operating

PRODUCT

FAMILY

OPERATING

Vcc

( ICCSB1, Max )

( ICC, Max )

PKG TYPE

DICE

TSOP1-48

BGA-48-0608

DICE

TEMPERATURE

RANGE

Vcc=3.0V

8uA

Vcc=3.0V

30mA

BS616LV2012DC

BS616LV2012TC

BS616LV2012AC

BS616LV2012DI

BS616LV2012TI

+0 ^OC to +70 ^O

-40 ^OC to +85 ^O

2.7V ~ 3.6V

70 / 100

TSOP1-48

70 / 100

12uA

35mA

BS616LV2012AI

BGA-48-0608

PIN CONFIGURATIONS

BLOCK DIAGRAM

A13

A15

A16

A14

Address

1024

Input

Row

Decoder

Memory Array

1024 x 2048

A12

N.C.

Buffer

2048

D10

Data

Column I/O

Input

DQ0

VSS

VCC

D11

D12

N.C.

A14

VCC

VSS

Buffer

Write Driver

Sense Amp

A16

A15

A13

A10

128

Data

Output

D14

D13

Buffer

Column Decoder

DQ15

N.C.

D15

N.C.

A12

A11

N.C.

Control

Address Input Buffer

A11 A9 A3 A2 A1

A0 A10

Vcc

Gnd

48-ball BGA top view

Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.

Revision 2.4

April 2002

R0201-BS616LV2012

12 3 4 5 6 7...10

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