Datasheet > AZ100ELT21TR1

AZ100ELT21TR1

更新时间： 2024-09-18 06:38:51

品牌	Logo	应用领域
其他 - ETC		转换器接口集成电路光电二极管
页数	文件大小	规格书
5页	146K
描述
Differential PECL to CMOS/TTL Translator

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数据手册

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AZ100ELT21TR1 数据手册

ARIZONA MICROTEK, INC.

AZ100ELT21

Differential PECL to CMOS/TTL Translator

FEATURES

PACKAGE AVAILABILITY

•

3.5ns Typical Propagation Delay

Differential PECL Inputs

PACKAGE

SOIC 8

SOIC 8 T&R

TSSOP 8

PART NO.

MARKING

CMOS/TTL Outputs

AZ100ELT21D

AZM100ELT21

Flow Through Pinouts

AZ100ELT21DR1 AZM100ELT21

AZ100ELT21DR2 AZM100ELT21

AZ100ELT21T

Operating Range of 3.0V to 5.5V

Direct Replacement for ON Semiconductor

MC100ELT21

AZHLT21

TSSOP 8 T&R AZ100ELT21TR1

TSSOP 8 T&R AZ100ELT21TR2

•

Use AZ100ELT21 for 10K Applications

DESCRIPTION

The AZ100ELT21 is a differential PECL to CMOS/TTL translator. Because PECL (Positive ECL) levels are

used, only V_CCand ground are required. The small outline 8-lead packaging and the single gate of the ELT21 makes

it ideal for those applications where space, performance and low power are at a premium.

The ELT21 provides a V_BBoutput for single-ended use or a DC bias reference for AC coupling to the device.

For single-ended input applications, the V_BBreference should be connected to one side of the D0/D¯¯0 differential

input pair. The input signal is then fed to the other D0/D¯¯0 input. The V_BBpin should be used only as a bias for the

ELT21 as its sink/source capability is limited. When used, the V_BBpin should be bypassed to ground via a 0.01µF

capacitor.

NOTE: Specification in ECL/PECL tables are valid when thermal equilibrium is established.

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

PIN DESCRIPTION

FUNCTION

CMOS/TTL

CMOS/TTL Output

Differential Inputs

Positive Supply

Reference Voltage Output

Ground

D0, D¯¯0

V_CC

PECL

V_BB

GND

No Connect

GND

1630 S. STAPLEY DR., SUITE 125 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541

www.azmicrotek.com

12 3 4 5

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