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AZ100EP16FET

更新时间： 2024-09-18 04:33:23
品牌 Logo 应用领域
AZM 驱动器放大器
页数 文件大小 规格书
5页 71K
描述
ECL/PECL High Speed VCSEL Driver with Variable Output Swing or Limiting Amplifier

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AZ100EP16FET 技术参数

是否Rohs认证： 不符合生命周期：Contact Manufacturer
包装说明：TSSOP, TSSOP8,.19Reach Compliance Code：compliant
风险等级：5.92JESD-30 代码：R-PDSO-G8
JESD-609代码：e0标称负供电电压：-3.3 V
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP8,.19
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源：+-3.3 V认证状态：Not Qualified
子类别：Display Drivers标称供电电压：3.3 V
表面贴装：YES技术：ECL100K
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL

AZ100EP16FET 数据手册

 浏览型号AZ100EP16FET的Datasheet PDF文件第2页浏览型号AZ100EP16FET的Datasheet PDF文件第3页浏览型号AZ100EP16FET的Datasheet PDF文件第4页浏览型号AZ100EP16FET的Datasheet PDF文件第5页 
ARIZONA MICROTEK, INC.  
AZ100EP16FE  
ECL/PECL High Speed VCSEL Driver with  
Variable Output Swing or Limiting Amplifier  
PACKAGE AVAILABILITY  
FEATURES  
PACKAGE  
PART NUMBER  
MARKING  
AZHP  
16FE  
NOTES  
•
Silicon-Germanium for High Speed  
Operation  
<100ps Typical Rise/Fall Times  
Optimized for 0.622 to 2.5Gbps  
Fiber Applications  
S-Parameter (.s2p) and IBIS Model  
Files available on Arizona Microtek  
Website  
TSSOP 8  
AZ100EP16FET  
1,2  
•
•
1
2
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape  
& Reel.  
Date code on underside of part. Format: “Y” or “YY” for year followed by “WW”  
for week.  
•
DESCRIPTION  
The AZ100EP16FE is a Silicon–Germanium (SiGe) differential VCSEL driver with variable output swing or  
limiting post amplifier. The 100EP16FE is optimized for OC-12, OC-24, OC-48, Ethernet, Sonnet, Fiber Channel or  
related applications at data rates up to 2.5Gbps. An input controls the amplitude of the Q/Q¯ outputs, which allows  
compensation for differing VCSEL characteristics.  
The operational range of the 100EP16FE control input, VCTRL, is from VREF (full swing) to VCC (small swing).  
For post amplifier applications, maximum swing is achieved by leaving the VCTRL pin open or by tying it to the  
negative supply pin (VEE). Simple control of the output swing can be obtained by a variable resistor between the  
VREF and VCC pins, with the wiper driving VCTRL. A typical application circuit is described in this Data Sheet.  
The 100EP16FE also provides a VREF output which functions as a DC bias for input AC coupling to the device.  
The VREF pin should be used only as a bias for the 100EP16FE as its current sink/source capability is limited. When  
used, the VREF pin should be bypassed to ground via a 0.01μF capacitor.  
The maximum DC output current should be kept below 16mA. Connecting each output (Q/Q¯) to VEE with a  
180Ω resistor is typically used. The load is then AC coupled from the output. DC and AC symmetrical loading of  
the Q/Q¯ outputs will provide the best output wave shape.  
Under open input conditions for D/D¯, the Q/Q¯ outputs are not guaranteed.  
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.  
1
2
8
PIN DESCRIPTION  
VCTRL  
VCC  
PIN  
D, D¯  
VCTRL  
Q, Q¯  
VREF  
VCC  
FUNCTION  
Data Inputs  
Output Swing Control  
Data Outputs  
Reference Voltage Output  
Positive Supply  
7
6
5
D
Q
3
4
Q
D
VREF  
VEE  
VEE  
Negative Supply  
TSSOP 8  
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541  
www.azmicrotek.com  
12345

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