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AT28BV256-20SU-T PDF预览

AT28BV256-20SU-T

更新时间: 2024-11-28 14:47:51
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管内存集成电路
页数 文件大小 规格书
17页 221K
描述
200NS, SOIC, IND TEMP, GREEN

AT28BV256-20SU-T 技术参数

生命周期:Active包装说明:SOP,
Reach Compliance Code:compliant风险等级:2.18
最长访问时间:200 ns其他特性:THE PART EXISTS IN EEPROM3V
JESD-30 代码:R-PDSO-G28长度:17.9 mm
内存密度:262144 bit内存集成电路类型:EEPROM
内存宽度:8功能数量:1
端子数量:28字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:32KX8封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
编程电压:3 V座面最大高度:2.65 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:7.5 mm
Base Number Matches:1

AT28BV256-20SU-T 数据手册

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Features  
Single 2.7V - 3.6V Supply  
Fast Read Access Time – 200 ns  
Automatic Page Write Operation  
– Internal Address and Data Latches for 64 Bytes  
– Internal Control Timer  
Fast Write Cycle Times  
– Page Write Cycle Time: 10 ms Maximum  
– 1- to 64-byte Page Write Operation  
Low Power Dissipation  
256K (32K x 8)  
Battery-Voltage  
Parallel  
– 15 mA Active Current  
– 20 µA CMOS Standby Current  
Hardware and Software Data Protection  
Data Polling for End of Write Detection  
High Reliability CMOS Technology  
– Endurance: 10,000 Cycles  
EEPROMs  
– Data Retention: 10 Years  
JEDEC Approved Byte-wide Pinout  
Industrial Temperature Ranges  
Green (Pb/Halide-free) Packaging Option Only  
AT28BV256  
1. Description  
The AT28BV256 is a high-performance electrically erasable and programmable read-  
only memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac-  
tured with Atmel’s advanced nonvolatile CMOS technology, the device offers access  
times to 200 ns with power dissipation of just 54 mW. When the device is deselected,  
the CMOS standby current is less than 200 µA.  
The AT28BV256 is accessed like a Static RAM for the read or write cycle without the  
need for external components. The device contains a 64-byte page register to allow  
writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to  
64 bytes of data are internally latched, freeing the address and data bus for other  
operations. Following the initiation of a write cycle, the device will automatically write  
the latched data using an internal control timer. The end of a write cycle can be  
detected by Data polling of I/O7. Once the end of a write cycle has been detected a  
new access for a read or write can begin.  
Atmel’s AT28BV256 has additional features to ensure high quality and manufactura-  
bility. The device utilizes internal error correction for extended endurance and  
improved data retention characteristics. An optional software data protection mecha-  
nism is available to guard against inadvertent writes. The device also includes an  
extra 64 bytes of EEPROM for device identification or tracking.  
0273K–PEEPR–2/09  

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