April 2002
Preliminary
AS7C33512PFS16A
AS7C33512PFS18A
®
3.3V 512K × 16/18 pipeline burst synchronous SRAM
Features
• Asynchronous output enable control
• Available in 100-pin TQFP and 119-ball BGA package
• Byte write enables
• Multiple chip enables for easy expansion
• 3.3V core power supply
• Organization: 524,288 words × 16 or 18 bits
• Fast clock speeds to 166 MHz in LVTTL/LVCMOS
• Fast clock to data access: 3.5/3.8/4.0/5.0 ns
• Fast OE access time: 3.5/3.8/4.0/5.0 ns
• Fully synchronous register-to-register operation
• Single register “Flow-through” option
• Single-cycle deselect
- Dual-cycle deselect also available (AS7C33512PFD16A/
AS7C33512PFD18A)
• 2.5V or 3.3V I/O operation with separate V
DDQ
• 30 mW typical standby power in power down mode
1
• NTD™ pipeline architecture available
(AS7C33512NTD16A/AS7C33512NTD18A)
• Available in both 2 chip enable and 3 chip enable
- 2 CE part number is AS7C33512PFS16A or AS7C33512PFS18A2
®
1
1. Pentium is a registered trademark of Intel Corporation. NTD™ is a
• Pentium® compatible architecture and timing
trademark of Alliance Semiconductor Corporation. All trademarks men-
tioned in this document are the property of their respective owners.
Logic block diagram
LBO
Burst logic
CLK
ADV
ADSC
ADSP
CLK
CS
CLR
512K × 16/18
Memory
19 17
19
19
AddresQs
register
D
array
A[18:0]
CS
CLK
16/18
16/18
GWE
D
Q
DQb
BW
b
Byte Write
registers
BWE
CLK
D
Q
DQa
2
BW
a
Byte Write
CLK
registers
CE0
CE1
CE2
OE
D EnableQ
register
Input
Output
registers
registers
CE
CLK
CLK
CLK
D EnableQ
delay
Power
down
ZZ
register
CLK
OE
16/18
DQ[a,b]
FT
Selection guide
–166
–150
6.6
–133
7.5
133
4
–100
10
Units
ns
Minimum cycle time
6
Maximum pipelined clock frequency
Maximum pipelined clock access time
Maximum operating current
166
3.5
475
130
30
150
3.8
100
5
MHz
ns
450
110
30
425
100
30
325
90
mA
mA
mA
Maximum standby current
Maximum CMOS standby current (DC)
30
4/15/02; v.1.5
Alliance Semiconductor
1 of 14
Copyright © Alliance Semiconductor. All rights reserved.