Datasheet > AS7C33512PFS16A2-100BC

AS7C33512PFS16A2-100BC

更新时间： 2022-12-01 19:28:13

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
14页	370K
描述
SRAM

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AS7C33512PFS16A2-100BC 数据手册

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AS7C33512PFS16A

AS7C33512PFS18A

Signal descriptions

Signal

I/O

Properties

CLOCK

SYNC

Description

CLK

Clock. All inputs except OE, FT, ZZ, LBO are synchronous to this clock.

Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.

Data. Driven as output when the chip is enabled and OE is active.

A0–A18

DQ[a,b]

I/O

SYNC

Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When

CE0 is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more

information.

CE0

SYNC

Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on

clock edges when ADSC is active or when CE0 and ADSP are active.

CE1, CE2

ADSP

SYNC

Address strobe (processor). Asserted LOW to load a new address or to enter standby

mode.

Address strobe (controller). Asserted LOW to load a new address or to enter standby

mode.

ADSC

ADV

SYNC

Burst advance. Asserted LOW to continue burst read/write.

Global write enable. Asserted LOW to write all 16/18 bits. When HIGH, BWE and

BW[a,b] control write enable.

GWE

Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a,b]

inputs.

BWE

BW[a,b]

SYNC

Write enables. Used to control write of individual bytes when GWE = HIGH and

BWE = LOW. If any of BW[a,b] is active with GWE = HIGH and BWE = LOW the

cycle is a write cycle. If all BW[a,b] are inactive, the cycle is a read cycle.

Asynchronous output enable. I/O pins are driven when OE is active and the chip is

in read mode.

ASYNC

STATIC

Count mode. When driven HIGH, count sequence follows Intel XOR convention.

When driven LOW, count sequence follows linear convention. This signal is

internally pulled HIGH.

LBO

Flow-through mode.When LOW, enables single register flow-through mode.

Connect to V_DDif unused or for pipelined operation.

STATIC

ASYNC

Snooze. Places device in low power mode; data is retained. Connect to GND if

unused.

Absolute maximum ratings

Parameter

Symbol

V_DD, V_DDQ

V_IN

Min

–0.5

–

Max

+4.6

Unit

Power supply voltage relative to GND

Input voltage relative to GND (input pins)

Input voltage relative to GND (I/O pins)

Power dissipation

V_DD+ 0.5

V_DDQ+ 0.5

1.8

V_IN

P_D

°C

DC output current

I_OUT

–

Storage temperature (plastic)

Temperature under bias

T_stg

–65

+150

T_bias

+135

Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional opera-

tion of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions may affect reliability.

4/15/02; v.1.5

Alliance Semiconductor

5 of 14

1 2 3 456 7 8...14

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与AS7C33512PFS16A2-100BC相关器件

型号	品牌	描述	获取价格	数据表
AS7C33512PFS16A2-100BI	ISSI	SRAM	获取价格
AS7C33512PFS16A2-100TQC	ALSC	Standard SRAM, 512KX16, 12ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100	获取价格
AS7C33512PFS16A2-100TQI	ALSC	Standard SRAM, 512KX16, 12ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100	获取价格
AS7C33512PFS16A2-133BC	ISSI	SRAM	获取价格
AS7C33512PFS16A2-133TQC	ALSC	Standard SRAM, 512KX16, 10ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100	获取价格
AS7C33512PFS16A2-133TQI	ISSI	Standard SRAM, 512KX16, 10ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100	获取价格

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