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AS7C33512PFS18A-100TQIN PDF预览

AS7C33512PFS18A-100TQIN

更新时间: 2024-10-28 19:56:07
品牌 Logo 应用领域
ALSC 时钟ISM频段静态存储器内存集成电路
页数 文件大小 规格书
16页 441K
描述
Standard SRAM, 512KX18, 12ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100

AS7C33512PFS18A-100TQIN 数据手册

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May 2004  
AS7C33512PFS18A  
®
3.3V 512K × 18 pipeline burst synchronous SRAM  
Features  
• Available in 100-pin TQFP package  
• Organization: 524,288 words × 18 bits  
• Fast clock speeds to 166 MHz in LVTTL/LVCMOS  
• Fast clock to data access: 3.5/3.8/4.0/5.0 ns  
• Fast OE access time: 3.5/3.8/4.0/5.0 ns  
• Fully synchronous register-to-register operation  
• Single register “Flow-through” option  
• Byte write enables  
• Multiple chip enables for easy expansion  
• 3.3V core power supply  
• 2.5V or 3.3V I/O operation with separate V  
DDQ  
• 30 mW typical standby power in power down mode  
2
• NTD™ pipeline architecture available  
• Single-cycle deselect  
(AS7C33512NTD18A)  
- Dual-cycle deselect also available (AS7C33512PFD18A)  
1
• Pentium® compatible architecture and timing  
• Asynchronous output enable control  
2. NTD™ is a trademark of Alliance Semiconductor Corporation.  
All trademarks mentioned in this document are the property of their  
respective owners.  
1. Pentium® is a registered trademark of Intel Corporation.  
Logic block diagram  
LBO  
Burst logic  
CLK  
CLK  
CS  
CLR  
ADV  
ADSC  
ADSP  
512K × 18  
Memory  
array  
19 17  
19  
19  
Q
D
A[18:0]  
Address  
register  
CS  
CLK  
18  
18  
2
GWE  
BWb  
D
Q
DQb  
Byte Write  
registers  
BWE  
BWa  
CLK  
D
Q
DQa  
Byte Write  
registers  
CLK  
CE0  
CE1  
OE  
Output  
D
Q
Q
Input  
registers  
Enable  
register  
CE  
CLK  
CE2  
registers  
CLK  
CLK  
D
Enable  
delay  
register  
CLK  
Power  
down  
ZZ  
OE  
18  
DQ[a,b]  
FT  
Selection guide  
–166  
–150  
6.6  
–133  
7.5  
133  
4
–100  
10  
Units  
ns  
Minimum cycle time  
6
Maximum pipelined clock frequency  
Maximum pipelined clock access time  
Maximum operating current  
166  
3.5  
475  
130  
30  
150  
3.8  
100  
5
MHz  
ns  
450  
110  
30  
425  
100  
30  
325  
90  
mA  
mA  
mA  
Maximum standby current  
Maximum CMOS standby current (DC)  
30  
5/7/04; v.2.1  
Alliance Semiconductor  
1 of 16  
Copyright © Alliance Semiconductor. All rights reserved.  

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