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AS7C33512PFS18A-166TQC PDF预览

AS7C33512PFS18A-166TQC

更新时间: 2024-02-13 08:12:25
品牌 Logo 应用领域
ALSC 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
20页 512K
描述
3.3V 512K x 18 pipeline burst synchronous SRAM

AS7C33512PFS18A-166TQC 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP,针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.35
最长访问时间:4 ns其他特性:PIPELINED ARCHITECTURE
JESD-30 代码:R-PQFP-G100JESD-609代码:e3
长度:20 mm内存密度:9437184 bit
内存集成电路类型:STANDARD SRAM内存宽度:18
功能数量:1端子数量:100
字数:524288 words字数代码:512000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:512KX18
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):245
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

AS7C33512PFS18A-166TQC 数据手册

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November 2004  
AS7C33512PFS18A  
®
3.3V 512K × 18 pipeline burst synchronous SRAM  
Features  
• Multiple chip enables for easy expansion  
• 3.3V core power supply  
• 2.5V or 3.3V I/O operation with separate V  
• 30 mW typical standby power in power down mode  
• Linear or interleaved burst control  
• Snooze mode for reduced power-standby  
• Common data inputs and data outputs  
• Organization: 524,288 words × 18 bits  
• Fast clock speeds to 166 MHz  
• Fast clock to data access: 3.5/4.0 ns  
• Fast OE access time: 3.5/4.0 ns  
• Fully synchronous register-to-register operation  
• Single-cycle deselect  
• Asynchronous output enable control  
• Available in 100-pin TQFP package  
• Individual byte write and global write  
DDQ  
Logic block diagram  
LBO  
Burst logic  
CLK  
ADV  
CLK  
CS  
CLR  
ADSC  
ADSP  
512K × 18  
Memory  
array  
19 17  
19  
19  
Q
D
A[18:0]  
Address  
register  
CS  
CLK  
18  
18  
2
GWE  
BWb  
D
Q
DQb  
Byte Write  
registers  
BWE  
BWa  
CLK  
D
Q
DQa  
Byte Write  
registers  
CLK  
CE0  
CE1  
OE  
Output  
D
Q
Q
Input  
registers  
Enable  
register  
CE  
CLK  
CE2  
registers  
CLK  
CLK  
D
Enable  
delay  
register  
CLK  
Power  
down  
ZZ  
OE  
18  
DQ[a,b]  
Selection guide  
–166  
6
–133  
7.5  
133  
4
Units  
ns  
Minimum cycle time  
Maximum clock frequency  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
Maximum CMOS standby current (DC)  
166  
3.5  
475  
130  
30  
MHz  
ns  
425  
100  
30  
mA  
mA  
mA  
11/30/04; v.2.2  
Alliance Semiconductor  
1 of 20  
Copyright © Alliance Semiconductor. All rights reserved.  

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