Datasheet > AS7C33512PFS16A-150BC

AS7C33512PFS16A-150BC

更新时间： 2024-01-15 11:17:55

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器内存集成电路
页数	文件大小	规格书
14页	370K
描述
Standard SRAM, 512KX16, 10ns, CMOS, PBGA119, 14 X 20 MM, BGA-119

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AS7C33512PFS16A-150BC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	LBGA,	针数：	119
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.64
最长访问时间：	10 ns	其他特性：	FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 代码：	R-PBGA-B119	JESD-609代码：	e0
长度：	22 mm	内存密度：	8388608 bit
内存集成电路类型：	STANDARD SRAM	内存宽度：	16
功能数量：	1	端子数量：	119
字数：	524288 words	字数代码：	512000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	512KX16
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	座面最大高度：	1.7 mm
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	TIN LEAD	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

AS7C33512PFS16A-150BC 数据手册

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AS7C33512PFS16A

AS7C33512PFS18A

Functional description

The AS7C33512PFS16A and AS7C33512PFS18A are high performance CMOS 8-Mbit synchronous Static Random Access Memory (SRAM)

devices organized as 524,288 words × 16 or 18 bits and incorporate a pipeline for highest frequency on any given technology.

Timing for this device is compatible with existing Pentium synchronous cache specifications. This architecture is suited for ASIC, DSP

™

(TMS320C6X), and PowerPC -based systems in computing, datacom, instrumentation, and telecommunications systems.

Fast cycle times of 6/6.6/7.5/10 ns with clock access times (t ) of 3.5/3.8/4.0/5.0 ns enable 166, 150, 133 and 100 MHz bus frequencies.

Three chip enable inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC),

or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.

Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register.

When ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data

accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven

on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted but is sampled on all

subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled LOW and both address strobes

®1

are HIGH. Burst mode is selectable with the LBO input. With LBO unconnected or driven HIGH, burst operations use a Pentium count

™

sequence. With LBO driven LOW the device uses a linear count sequence suitable for PowerPC and many other applications.

Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 16/

18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting

BWE and the appropriate individual byte BWn signal(s).

BWn is ignored on the clock edge that samples ADSP LOW, but is sampled on all subsequent clock edges. Output buffers are disabled when

BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled LOW. Address is incremented

internally to the next burst address if BWn and ADV are sampled LOW.

Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.

•

ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC

WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).

• Master chip select CE0 blocks ADSP, but not ADSC

The AS7C33512PFS16A and AS7C33512PFS18A operate from a 3.3V supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V.

These devices are available in a 100-pin 14×20 mm TQFP and 119-ball BGA packaging.

Capacitance

Parameter

Input capacitance

I/O capacitance

Symbol

C_IN

Signals

Address and control pins

I/O pins

Test conditions

V_IN= 0V

Max

Unit

C_I/O

V_IN= V_OUT= 0V

Write enable truth table (per byte)

GWE

BWE

BWn

WEn

Key: X = Don’t Care, L = Low, H = High, T=True, F=False; * valid read; n = a,b; WE, WEn = internal write signal

Burst Order

Interleaved Burst Order

Linear Burst Order

LBO=0

LBO=1

Starting Address 00

First increment 01

Second increment 10

Third increment 11

Starting Address 00

First increment 01

Second increment 10

Third increment 11

™

1. PowerPC is a trademark International Business Machines Corporation

4/15/02; v.1.5

Alliance Semiconductor

4 of 14

1 2 345 6 7...14

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与AS7C33512PFS16A-150BC相关器件

型号	品牌	描述	获取价格	数据表
AS7C33512PFS16A-150BI	ISSI	Standard SRAM, 512KX16, 10ns, CMOS, PBGA119, 14 X 20 MM, BGA-119	获取价格
AS7C33512PFS16A-150TQC	ISSI	Standard SRAM, 512KX16, 10ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100	获取价格
AS7C33512PFS16A-150TQI	ISSI	Standard SRAM, 512KX16, 10ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100	获取价格
AS7C33512PFS16A-166BC	ISSI	Standard SRAM, 512KX16, 9ns, CMOS, PBGA119, 14 X 20 MM, BGA-119	获取价格
AS7C33512PFS16A-166BI	ISSI	Standard SRAM, 512KX16, 9ns, CMOS, PBGA119, 14 X 20 MM, BGA-119	获取价格
AS7C33512PFS16A-166TQC	ISSI	Standard SRAM, 512KX16, 9ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100	获取价格

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