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AS7C33256NTD32A-166HTQI PDF预览

AS7C33256NTD32A-166HTQI

更新时间: 2024-11-03 20:59:27
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
12页 194K
描述
ZBT SRAM, 256KX32, 9ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100

AS7C33256NTD32A-166HTQI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP,针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.64
最长访问时间:9 ns其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 代码:R-PQFP-G100JESD-609代码:e0
长度:20 mm内存密度:8388608 bit
内存集成电路类型:ZBT SRAM内存宽度:32
功能数量:1端子数量:100
字数:262144 words字数代码:256000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:256KX32
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

AS7C33256NTD32A-166HTQI 数据手册

 浏览型号AS7C33256NTD32A-166HTQI的Datasheet PDF文件第2页浏览型号AS7C33256NTD32A-166HTQI的Datasheet PDF文件第3页浏览型号AS7C33256NTD32A-166HTQI的Datasheet PDF文件第4页浏览型号AS7C33256NTD32A-166HTQI的Datasheet PDF文件第5页浏览型号AS7C33256NTD32A-166HTQI的Datasheet PDF文件第6页浏览型号AS7C33256NTD32A-166HTQI的Datasheet PDF文件第7页 
May 2002  
AS7C33256NTD32A  
AS7C33256NTD36A  
&
1
TM  
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Features  
• Organization: 262,144 words × 32 or 36 bits  
• NTD architecture for efficient bus operation  
Available in 100-pin TQFP  
Byte write enables  
™1  
Fast clock speeds to 166 MHz in LVTTL/ LVCMOS  
Fast clock to data access: 3.0/ 3.5/ 3.8/ 4/ 5 ns  
Fast OEaccess time: 3.5/ 3.8/ 4/ 5 ns  
Fully synchronous operation  
Clock enable for operation hold  
• Multiple chip enables for easy expansion  
• 3.3 core power supply  
• 2.5V or 3.3V I/ O operation with separate V  
DDQ  
• “Flow-through” or “pipelined” mode  
Asynchronous output enable control  
• 30 mW typical standby power  
Self-timed write cycles  
• Interleaved or linear burst modes  
Snooze mode for standby operation  
1. NTD is a trademark of Alliance Semiconductor Corporation.  
Logic block diagram  
18  
18  
Q
D Address  
register  
Burst logic  
A[17:0]  
CLK  
D
Q
CE0  
CE1  
CE2  
Write delay  
addr. registers  
CLK  
18  
R/W  
BWa  
BWb  
BWc  
Control  
logic  
CLK  
BWd  
256K x 32/ 36  
SRAM  
ADV / LD  
FT  
LBO  
ZZ  
CLK  
Array  
36/ 32  
36/ 32  
Data  
Register  
CLK  
DATA [a:d]  
Q
D Input  
36/ 32  
36/ 32  
36/ 32  
CLK  
CEN  
CLK  
Output  
Register  
OE  
36/ 32  
DATA [a:d]  
OE  
Selection guide  
-166  
6
-150  
6.7  
-133  
7.5  
133  
4
-100  
10  
Units  
ns  
Minimum cycle time  
Maximum pipelined clock frequency  
Maximum pipelined clock access time  
Maximum operating current  
166  
3.0/ 3.51  
150  
3.8  
100  
5
MHz  
ns  
475  
425  
110  
30  
400  
100  
30  
300  
90  
mA  
mA  
mA  
Maximum standby current  
130  
Maximum CMOS standby current (DC)  
30  
30  
1 3.0 ns available on 166 MHz parts with “H” suffix. For further information see page 7 and last page with ordering codes.  
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