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AS7C33256NTD36A-133TQCN PDF预览

AS7C33256NTD36A-133TQCN

更新时间: 2024-11-02 23:00:31
品牌 Logo 应用领域
ALSC 存储内存集成电路静态存储器
页数 文件大小 规格书
19页 441K
描述
3.3V 256K x 2/36 Pipelined burst Synchronous SRAM with NTD

AS7C33256NTD36A-133TQCN 数据手册

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AS7C33256NTD32A  
AS7C33256NTD36A  
November 2004  
®
3.3V 256K×32/36 Pipelined burst Synchronous SRAM with NTDTM  
Features  
• Organization: 262,144 words × 32 or 36 bits  
• NTDarchitecture for efficient bus operation  
• Fast clock speeds to 166 MHz  
• Clock enable for operation hold  
• Multiple chip enables for easy expansion  
• 3.3 core power supply  
• Fast clock to data access: 3.5/4.0 ns  
• Fast OE access time: 3.5/4.0 ns  
• Fully synchronous operation  
• Common data inputs and data outputs  
• Asynchronous output enable control  
• Available in 100-pin TQFP  
• 2.5V or 3.3V I/O operation with separate VDDQ  
• Self-timed write cycles  
• Interleaved or linear burst modes  
• Snooze mode for standby operation  
• Byte write enables  
Logic Block Diagram  
18  
18  
Q
DAddress  
register  
Burst logic  
A[17:0]  
CLK  
D
Q
CE0  
CE1  
CE2  
Write delay  
addr. registers  
CLK  
18  
R/W  
BWa  
BWb  
BWc  
Control  
logic  
CLK  
BWd  
256K x 32/36  
SRAM  
ADV / LD  
LBO  
ZZ  
CLK  
Array  
36/32  
36/32  
Data  
DQ [a:d]  
Q
D Input  
Register  
CLK  
36/32  
36/32  
36/32  
CLK  
CEN  
CLK  
Output  
Register  
OE  
36/32  
DQ[a:d]  
OE  
Selection Guide  
-166  
6
-133  
7.5  
133  
4
Units  
ns  
Minimum cycle time  
Maximum clock frequency  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
166  
3.5  
475  
130  
30  
MHz  
ns  
400  
100  
30  
mA  
mA  
mA  
Maximum CMOS standby current (DC)  
11/30/04, v. 2.1  
Alliance Semiconductor  
P. 1 of 19  
Copyright © Alliance Semiconductor. All rights reserved.  

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