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AS5SS256K18DQ-8IT

更新时间： 2024-11-07 03:11:31
品牌 Logo 应用领域
AUSTIN 静态存储器
页数 文件大小 规格书
13页 217K
描述
256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through

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AS5SS256K18DQ-8IT 数据手册

 浏览型号AS5SS256K18DQ-8IT的Datasheet PDF文件第2页浏览型号AS5SS256K18DQ-8IT的Datasheet PDF文件第3页浏览型号AS5SS256K18DQ-8IT的Datasheet PDF文件第4页浏览型号AS5SS256K18DQ-8IT的Datasheet PDF文件第5页浏览型号AS5SS256K18DQ-8IT的Datasheet PDF文件第6页浏览型号AS5SS256K18DQ-8IT的Datasheet PDF文件第7页 
SSRAM  
AS5SS256K18  
Austin Semiconductor, Inc.  
256K x 18 SSRAM  
PIN ASSIGNMENT  
Synchronous Burst SRAM,  
(Top View)  
Flow-Through  
FEATURES  
100-pinTQFP  
• Fast access times: 8, 10, and 15ns  
• Fast clock speed: 113, 100, and 66 MHz  
• Fast clock and OE\ access times  
• Single +3.3V +0.3V/-0.165V power supply (VDD  
• SNOOZE MODE for reduced-power standby  
• Common data inputs and data outputs  
• Individual BYTE WRTIE control and GLOBAL WRITE  
• Three chip enables for simple depth expansion and address  
pipelining  
• Clock-controlled and registered addresses, data I/Os and  
control signals  
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81  
NC  
NC  
NC  
DDQ  
VSS  
NC  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
SA  
NC  
NC  
VDD  
VSS  
NC  
DQPa  
DQa  
DQa  
VSS  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
)
V
Q
NC  
DQb  
DQb  
VSS  
VDD  
Q
DQb  
DQb  
VSS  
VDD  
Q
DQa  
DQa  
VSS  
NC  
VDD  
ZZ  
VDD  
NC  
VSS  
DQb  
DQb 19  
DDQ  
VSS 21  
DQb 22  
DQb  
• Interally self-timed WRITE cycle  
• Burst control pin (interleaved or linear burst)  
• Automatic power-down  
DQa  
DQa  
V
20  
VDD  
VSS  
DQa  
DQa  
NC  
NC  
VSS  
VDD  
NC  
NC  
NC  
Q
• Low capacitive bus loading  
• Operating Temperature Ranges:  
23  
- Military -55oC to +125oC  
DQPb 24  
NC 25  
- Industrial -40oC to +85oC  
VSS  
VDD  
26  
27  
Q
Q
NC 28  
NC  
NC 30  
OPTIONS  
• Timing  
MARKING  
29  
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50  
7.5ns/8ns/113 MHz  
8.5ns/10ns/100 MHz  
10ns/15ns/66 MHz  
• Packages  
-8*  
-9  
-10  
**pins 42,43 reserved for future address expansion for 8Mb, 16Mb densities.  
100-pin TQFP  
DQ No. 1001  
CE2), burst control inputs (ADSC\, ADSP\, ADV\), byte write enables  
(BWx\) and global write (GW\).  
• Operating Temperature Ranges:  
- Military -55oC to +125oC  
- Industrial -45oC to +85oC  
*available as IT only.  
IT  
XT  
Asynchronous inputs include the output enable (OE\), clock (CLK)  
and snooze enable (ZZ). There is also a burst mode input (MODE) that  
selects between interleaved and linear burst modes. The data-out (Q),  
enabled by OE\, is also asynchronous. WRITE cycles can be from one  
to two bytes wide, as controlled by the write control inputs.  
Burst operation can be initiated with either address status processor  
(ADSP\) or address status controller (ADSC\) inputs. Subsequent burst  
addresses can be internally generated as controlled by the burst ad-  
vance input (ADV\).  
For more products and information  
please visit our web site at  
www.austinsemiconductor.com  
Address and write control are registered on-chip to simplify WRITE  
cycles. This allows self-timed WRITE cycles. Individual byte enables  
allow individual bytes to be written. During WRITE cycles on this x18  
device BWa\ controls DQa pins and DQPa; BWb\ controls DQb pins  
and DQPb. GW\ LOW causes all bytes to be written. Parity bits are  
available on this device.  
ASI’s 4Mb Synchronous Burst SRAMs operate from a +3.3V VDD  
power supply, and all inputs and outputs are TTL-compatible. The de-  
vice is ideally suited for 486, Pentium®, and PowerPC systems and  
those systems that benefit from a wide synchronous data bus.  
GENERAL DESCRIPTION  
The Austin Semiconductor, Inc. Synchronous Burst SRAM family  
employs high-speed, low power CMOS designs that are fabricated us-  
ing an advanced CMOS process.  
ASI’s 4Mb Synchronous Burst SRAMs integrate a 256K x 18, SRAM  
core with advanced synchronous peripheral circuitry and a 2-bit burst  
counter. All synchronous inputs pass through registers controlled by a  
positive-edge-triggered single clock input (CLK). The synchronous  
inputs include all addresses, all data inputs, active LOW chip enable  
(CE\), two additional chip enables for easy depth expansion (CE2\,  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
AS5SS256K18  
Rev. 2.0 12/00  
1
1234567...13

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