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AS5SS256K36_05 PDF预览

AS5SS256K36_05

更新时间: 2024-09-17 06:37:55
品牌 Logo 应用领域
AUSTIN 静态存储器
页数 文件大小 规格书
16页 379K
描述
256K x 36 SSRAM Flow-Through, Synchronous Burst SRAM

AS5SS256K36_05 数据手册

 浏览型号AS5SS256K36_05的Datasheet PDF文件第2页浏览型号AS5SS256K36_05的Datasheet PDF文件第3页浏览型号AS5SS256K36_05的Datasheet PDF文件第4页浏览型号AS5SS256K36_05的Datasheet PDF文件第5页浏览型号AS5SS256K36_05的Datasheet PDF文件第6页浏览型号AS5SS256K36_05的Datasheet PDF文件第7页 
SSRAM  
AS5SS256K36 &  
AS5SS256K36A  
Austin Semiconductor, Inc.  
256K x 36 SSRAM  
Flow-Through, Synchronous  
Burst SRAM  
PIN ASSIGNMENT  
(Top View)  
100-pin TQFP (DQ)  
(2-chip enable version, “A” indicator)  
FEATURES  
z Organized 256K x 36  
z Fast Clock and OE\ access times  
z Single +3.3V +0.3V/-0.165V power supply (VDD)  
z SNOOZE MODE for reduced-power standby  
z Common data inputs and data outputs  
z Individual BYTE WRITE control and GLOBAL WRITE  
z Three chip enables for simple depth expansion and address  
pipelining  
DQPc  
DQc  
DQc  
VDDQ  
Vss  
DQc  
DQc  
DQc  
DQc  
Vss  
VDDQ  
DQc  
DQc  
Vss  
VDD  
NC  
1
2
3
4
5
6
7
8
8 0  
7 9  
7 8  
7 7  
7 6  
7 5  
7 4  
7 3  
7 2  
7 1  
7 0  
6 9  
6 8  
6 7  
6 6  
6 5  
6 4  
6 3  
6 2  
6 1  
6 0  
5 9  
5 8  
5 7  
5 6  
5 5  
5 4  
5 3  
5 2  
5 1  
DQPb  
DQb  
DQb  
VDDQ  
Vss  
DQb  
DQb  
DQb  
DQb  
Vss  
VDDQ  
DQb  
DQb  
Vss  
9
1 0  
1 1  
1 2  
1 3  
1 4  
1 5  
1 6  
1 7  
1 8  
1 9  
2 0  
2 1  
2 2  
2 3  
2 4  
2 5  
2 6  
2 7  
2 8  
2 9  
3 0  
z Clock-controlled and registered addresses, data I/Os and  
control signals  
NC  
VDD  
ZZ  
z Internally self-timed WRITE cycle  
z Burst control (interleaved or linear burst)  
z Automatic power-down for portable applications  
z 100-lead TQFP package for high density, high speed  
z Low capacitive bus loading  
Vss  
DQd  
DQd  
VDDQ  
Vss  
DQd  
DQd  
DQd  
DQd  
Vss  
VDDQ  
DQd  
DQd  
DQPd  
DQa  
DQa  
VDDQ  
Vss  
DQa  
DQa  
DQa  
DQa  
Vss  
VDDQ  
DQa  
DQa  
DQPa  
OPTIONS  
MARKING  
z Timing  
8.5ns/10ns/100MHz  
10ns/15ns/66MHz  
-8.5*  
-10  
z Packages  
100-pin TQFP (2-chip enable)  
z Pinout  
2-chip Enables  
DQ No. 1001  
100-pin TQFP (DQ)  
(3-chip enable version, no indicator)  
A (PRELIMINARY)  
no indicator  
3-chip Enables  
z Operating Temperature Ranges  
Military (-55oC to +125oC)  
Industrial (-40oC to +85oC)  
XT*  
IT  
DQPc  
DQc  
DQc  
VDDQ  
Vss  
DQc  
DQc  
DQc  
DQc  
Vss  
VDDQ  
DQc  
DQc  
Vss  
VDD  
NC  
1
2
3
4
5
6
7
8
DQPb  
DQb  
DQb  
VDDQ  
Vss  
DQb  
DQb  
DQb  
DQb  
Vss  
VDDQ  
DQb  
DQb  
Vss  
8 0  
7 9  
7 8  
7 7  
7 6  
7 5  
7 4  
7 3  
7 2  
7 1  
7 0  
6 9  
6 8  
6 7  
6 6  
6 5  
6 4  
6 3  
6 2  
6 1  
6 0  
5 9  
5 8  
5 7  
5 6  
5 5  
5 4  
5 3  
5 2  
5 1  
*NOTE: -8.5/XT combination not available.  
9
1 0  
1 1  
1 2  
1 3  
1 4  
1 5  
1 6  
1 7  
1 8  
1 9  
2 0  
2 1  
2 2  
2 3  
2 4  
2 5  
2 6  
2 7  
2 8  
2 9  
3 0  
GENERAL DESCRIPTION  
The AS5SS256K36 employs high-speed, low-power CMOS  
designs that are fabricated using an advanced CMOS process.  
This 8Mb Synchronous Burst SRAM integrates a 256K x 36  
SRAM core with advanced synchronous peripheral circuitry and a 2-bit  
burst counter. All synchronous inputs pass through registers controlled  
by a positive-edge-triggered single-clock input (CLK). The synchro-  
nous inputs include all addresses, all data inputs, active LOW chip en-  
able (CE\), two additional chip enables for easy depth expansion (CE2\,  
CE2), burst control inputs (ADSC\, ADSP\, ADV\), byte write enables  
(BWx\) and global write (GW\). Note that CE2\ is not available on the  
A version.  
NC  
VDD  
ZZ  
Vss  
DQd  
DQd  
VDDQ  
Vss  
DQd  
DQd  
DQd  
DQd  
Vss  
VDDQ  
DQd  
DQd  
DQPd  
DQa  
DQa  
VDDQ  
Vss  
DQa  
DQa  
DQa  
DQa  
Vss  
VDDQ  
DQa  
DQa  
DQPa  
For more products and information  
please visit our web site at  
www.austinsemiconductor.com  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
AS5SS256K36 &  
AS5SS256K36A  
Rev. 3.6 06/05  
1

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