SSRAM
AS5SS256K36 &
AS5SS256K36A
Austin Semiconductor, Inc.
256K x 36 SSRAM
PIN ASSIGNMENT
Synchronous Burst SRAM
(Top View)
FEATURES
100-pin TQFP (DQ)
(2-chip enable version, “A” indicator)
l Organized 256K x 36
l Fast Clock and OE\ access times
l Single +3.3V +0.3V/-0.165V power supply (VDD)
l SNOOZE MODE for reduced-power standby
l Common data inputs and data outputs
l Individual BYTE WRITE control and GLOBAL WRITE
l Three chip enables for simple depth expansion and address
pipelining
DQPc
DQc
DQc
VDDQ
Vss
DQc
DQc
DQc
DQc
Vss
VDDQ
DQc
DQc
Vss
VDD
NC
1
2
3
4
5
6
7
8
DQPb
DQb
DQb
VDDQ
Vss
DQb
DQb
DQb
DQb
Vss
VDDQ
DQb
DQb
Vss
8 0
7 9
7 8
7 7
7 6
7 5
7 4
7 3
7 2
7 1
7 0
6 9
6 8
6 7
6 6
6 5
6 4
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6
5 5
5 4
5 3
5 2
5 1
9
l Clock-controlled and registered addresses, data I/Os and
control signals
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
l Internally self-timed WRITE cycle
l Burst control (interleaved or linear burst)
l Automatic power-down for portable applications
l 100-lead TQFP package for high density, high speed
l Low capacitive bus loading
NC
VDD
ZZ
Vss
DQd
DQd
VDDQ
Vss
DQd
DQd
DQd
DQd
Vss
VDDQ
DQd
DQd
DQPd
DQa
DQa
VDDQ
Vss
DQa
DQa
DQa
DQa
Vss
VDDQ
DQa
DQa
DQPa
OPTIONS
l Timing
MARKING
8.5ns/10ns/100MHz
10ns/15ns/66MHz
l Packages
-8.5
-10
100-pin TQFP (2-chip enable)
l Pinout
2-chip Enables
DQ No. 1001
100-pin TQFP (DQ)
(3-chip enable version, no indicator)
A
3-chip Enables
no indicator
l Operating Temperature Ranges
Military (-55oC to +125oC)
Industrial (-40oC to +85oC)
XT
IT
DQPc
DQc
DQc
VDDQ
Vss
DQc
DQc
DQc
DQc
Vss
VDDQ
DQc
DQc
Vss
VDD
NC
1
2
3
4
5
6
7
8
DQPb
DQb
DQb
VDDQ
Vss
DQb
DQb
DQb
DQb
Vss
VDDQ
DQb
DQb
Vss
8 0
7 9
7 8
7 7
7 6
7 5
7 4
7 3
7 2
7 1
7 0
6 9
6 8
6 7
6 6
6 5
6 4
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6
5 5
5 4
5 3
5 2
5 1
GENERAL DESCRIPTION
9
The AS5SS256K36 employs high-speed, low-power CMOS
designs that are fabricated using an advanced CMOS process.
This 8Mb Synchronous Burst SRAM integrates a 256K x
36 SRAM core with advanced synchronous peripheral circuitry
and a 2-bit burst counter. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single-clock
input (CLK). The synchronous inputs include all addresses, all
data inputs, active LOW chip enable (CE\), two additional chip
enables for easy depth expansion (CE2\, CE2), burst control
inputs (ADSC\, ADSP\, ADV\), byte write enables (BWx\) and
global write (GW\). Note that CE2\ is not available on the A
version.
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
NC
VDD
ZZ
Vss
DQd
DQd
VDDQ
Vss
DQd
DQd
DQd
DQd
Vss
VDDQ
DQd
DQd
DQPd
DQa
DQa
VDDQ
Vss
DQa
DQa
DQa
DQa
Vss
VDDQ
DQa
DQa
DQPa
For more products and information
please visit our web site at
www.austinsemiconductor.com
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5SS256K36 &
AS5SS256K36A
Rev. 1.5 5/00
1
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