SSRAM
AS5SS256K18
256K x 18 SSRAM
Synchronous Burst SRAM,
Flow-Through
FEATURES
• Fast access times: 8, 10, and 15ns
• Fast clock speed: 113, 100, and 66 MHz
• Fast clock and OE\ access times
PIN ASSIGNMENT
(Top View)
100-pin TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
DDQ
VSS
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SA
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
• Single +3.3V ± 5% power supply (VDD
)
V
V
DDQ
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Individual BYTE WRTIE control and GLOBAL WRITE
• Three chip enables for simple depth expansion and address
pipelining
• Clock-controlled and registered addresses, data I/Os and
control signals
• Interally self-timed WRITE cycle
• Burst control pin (interleaved or linear burst)
• Automatic power-down
• Low capacitive bus loading
• Available in Industrial, Enhanced, and Mil-Temperature
Operating Ranges
• TQFP in copper lead frame for superior thermal
performance
• RoHs compliant options available
VSS
NC
DQPa
DQa
DQa
VSS
NC
DQb
DQb
VSS
VDD
Q
DQb
DQb
NC
VDD
NC
VDD
Q
DQa
DQa
VSS
NC
VDD
ZZ
VSS
DQb
DQb 19
DDQ 20
VSS 21
DQb 22
DQb 23
DQPb 24
NC 25
DQa
DQa
V
V
DDQ
VSS
DQa
DQa
NC
NC
VSS
VDD
NC
NC
NC
VSS 26
VDD
Q
27
Q
NC 28
NC 29
NC 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 4546 47 48 49 50
OPTIONS
• Timing
MARKING
7.5ns/8ns/113 MHz
8.5ns/10ns/100 MHz
10ns/15ns/66 MHz
• Packages
-8
-9
-10
**pins 42,43 reserved for future address expansion for 8Mb, 16Mb densities.
CE2), burst control inputs (ADSC\,ADSP\,ADV\), byte write enables
(BWx\) and global write (GW\).
TQFP
DQ No. 1001
DQC
DQCR
Asynchronous inputs include the output enable (OE\), clock (CLK)
and snooze enable (ZZ). There is also a burst mode input (MODE)
that selects between interleaved and linear burst modes. The data-out
(Q), enabled by OE\, is also asynchronous. WRITE cycles can be from
one to two bytes wide, as controlled by the write control inputs.
Burst operation can be initiated with either address status processor
(ADSP\) or address status controller (ADSC\) inputs. Subsequent
burst addresses can be internally generated as controlled by the burst
advance input (ADV\).
TQFP - Copper Lead Frame
TQFP - RoHS Compliant
• Operating Temperature Ranges:
- Military -55oC to +125oC
- Enhanced -45oC to +105oC
- Industrial -45oC to +85oC
/IT
/ET
/XT
Address and write control are registered on-chip to simplify WRITE
cycles. This allows self-timed WRITE cycles. Individual byte enables
allow individual bytes to be written. During WRITE cycles on this
x18 device BWa\ controls DQa pins and DQPa; BWb\ controls DQb
pins and DQPb. GW\ LOW causes all bytes to be written. Parity bits
are available on this device.
GENERAL DESCRIPTION
The Micross Components Synchronous Burst SRAM family
employs high-speed, low power CMOS designs that are fabricated
using an advanced CMOS process.
The 4Mb Synchronous Burst SRAMs integrate a 256K x 18, SRAM
core with advanced synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers controlled by
The 4Mb Synchronous Burst SRAMs operate from a +3.3V VDD
a positive-edge-triggered single clock input (CLK). The synchronous power supply, and all inputs and outputs are TTL-compatible. The
inputs include all addresses, all data inputs, active LOW chip enable device is ideally suited for 486, Pentium®, and PowerPC systems and
(CE\), two additional chip enables for easy depth expansion (CE2\, those systems that benefit from a wide synchronous data bus.
Micross Components reserves the right to change products or specifications without notice.
AS5SS256K18
Rev. 2.4 09/11
1
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