Datasheet > AS29LV800B-70RTC

AS29LV800B-70RTC

更新时间： 2024-01-16 17:35:09

品牌	Logo	应用领域
ANADIGICS		闪存可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
25页	440K
描述
3V 1M】8/512K】16 CMOS Flash EEPROM

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

AS29LV800B-70RTC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	TSOP1	包装说明：	TSOP1, TSSOP48,.8,20
针数：	48	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.32.00.51
风险等级：	5.28	最长访问时间：	70 ns
备用内存宽度：	8	启动块：	BOTTOM
命令用户界面：	YES	数据轮询：	YES
耐久性：	100000 Write/Erase Cycles	JESD-30 代码：	R-PDSO-G48
JESD-609代码：	e0	长度：	18.4 mm
内存密度：	8388608 bit	内存集成电路类型：	FLASH
内存宽度：	16	功能数量：	1
部门数/规模：	1,2,1,15	端子数量：	48
字数：	524288 words	字数代码：	512000
工作模式：	ASYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	512KX16
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSOP1
封装等效代码：	TSSOP48,.8,20	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	240	电源：	3.3 V
编程电压：	3 V	认证状态：	Not Qualified
就绪/忙碌：	YES	座面最大高度：	1.2 mm
部门规模：	16K,8K,32K,64K	最大待机电流：	0.000005 A
子类别：	Flash Memories	最大压摆率：	0.1 mA
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	切换位：	YES
类型：	NOR TYPE	宽度：	12 mm
Base Number Matches：	1

AS29LV800B-70RTC 数据手册

浏览型号AS29LV800B-70RTC的Datasheet PDF文件第10页

AS29LV800

March 2001

Item

Description

The unlock bypass feature increases the speed at which the system programs bytes or words to the

device because it bypasses the first two unlock cycles of the standard program command sequence.

To initiate the unlock bypass command sequence, two unlock cycles must be written, then

followed by a third cycle which has the unlock bypass command, 20h.

The device then begins the unlock bypass mode. In order to program in this mode, a two cycle

unlock bypass program sequence is required. The first cycle has the unlock bypass program

command, A0h. It is followed by a second cycle which has the program address and data. To

program additional data, the same sequence must be followed.

Unlock Bypass

Command Sequence

The unlock bypass mode has two valid commands, the Unlock Bypass Program command and the

Unlock Bypass Reset command. The only way the system can exit the unlock bypass mode is by

issuing the unlock bypass reset command sequence. This sequence involves two cycles. The first

cycle contains the data, 90h. The second cycle contains the data 00h. Addresses are don’t care for

both cycles. The device then returns to reading array data.

Chip erase requires six bus cycles: two unlock write cycles; a setup command, two additional

unlock write cycles; and finally the Chip Erase command.

Chip erase does not require logical 0s to be written prior to erasure. When the automated on-chip

erase algorithm is invoked with the Chip Erase command sequence, AS29LV800 automatically

programs and verifies the entire memory array for an all-zero pattern prior to erase. The 29LV800

returns to read mode upon completion of chip erase unless DQ5 is set high as a result of exceeding

time limit.

Chip Erase

Sector erase requires six bus cycles: two unlock write cycles, a setup command, two additional

unlock write cycles, and finally the Sector Erase command. Identify the sector to be erased by

addressing any location in the sector. The address is latched on the falling edge of WE; the

command, 30h is latched on the rising edge of WE. The sector erase operation begins after a sector

erase time-out.

To erase multiple sectors, write the Sector Erase command to each of the addresses of sectors to

erase after following the six bus cycle operation above. Timing between writes of additional sectors

must be less than the erase time-out period, or the AS29LV800 ignores the command and erasure

begins. During the time-out period any falling edge of WE resets the time-out. Any command

(other than Sector Erase or Erase Suspend) during time-out period resets the AS29LV800 to read

mode, and the device ignores the sector erase command string. Erase such ignored sectors by

restarting the Sector Erase command on the ignored sectors.

Sector Erase

The entire array need not be written with 0s prior to erasure. AS29LV800 writes 0s to the entire

sector prior to electrical erase; writing of 0s affects only selected sectors, leaving non-selected

sectors unaffected. AS29LV800 requires no CPU control or timing signals during sector erase

operations.

Automatic sector erase begins after sector erase time-out from the last rising edge of WE from the

sector erase command stream and ends when the DATA polling (DQ7) is logical 1. DATA polling

address must be performed on addresses that fall within the sectors being erased. AS29LV800

returns to read mode after sector erase unless DQ5 is set high by exceeding the time limit.

3/22/01; V.1.0

Alliance Semiconductor

P. 8 of 25

1...5 6 789 10 11...25

下载PDF

与AS29LV800B-70RTC相关器件

型号	品牌	描述	获取价格	数据表
AS29LV800B-70RTI	ANADIGICS	3V 1M】8/512K】16 CMOS Flash EEPROM	获取价格
AS29LV800B-70RTI	ALSC	Flash, 512KX16, 70ns, PDSO48, 12 X 20 MM, TSOP1-48	获取价格
AS29LV800B-80SC	ANADIGICS	3V 1M】8/512K】16 CMOS Flash EEPROM	获取价格
AS29LV800B-80SI	ANADIGICS	3V 1M】8/512K】16 CMOS Flash EEPROM	获取价格
AS29LV800B-80TC	ANADIGICS	3V 1M】8/512K】16 CMOS Flash EEPROM	获取价格
AS29LV800B-80TI	ANADIGICS	3V 1M】8/512K】16 CMOS Flash EEPROM	获取价格

与AS29LV800B-70RTC相关文章

STM32H743技术深度剖析与应用案例探索
2024-05-30

13
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
2024-05-30

13
74HC14芯片资料介绍：性能特性分析、引脚介绍
2024-05-30

11
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
2024-05-30

9

产品中心

服务支持

精选活动

关于我们

帮助中心

AS29LV800B-70RTC

AS29LV800B-70RTC 技术参数

AS29LV800B-70RTC 数据手册

与AS29LV800B-70RTC相关器件

与AS29LV800B-70RTC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

AS29LV800B-70RTC

AS29LV800B-70RTC 技术参数

AS29LV800B-70RTC 数据手册

与AS29LV800B-70RTC相关器件

与AS29LV800B-70RTC相关文章

您还可以找

您在本页遇到什么问题？