Philips Semiconductors
Application note
Using the P82B96 for bus interface
AN460
The P82B96 offers many different ways in which it can be used as a
bus interface. In its simplest application it can be used as an
interface between bus systems operating from different supply
voltages. Opto isolation between two bus systems is possible, and
also the availability of the Tx and Rx signals permits interfacing of
the P82B96 with other bus systems which separate the forward
output path, from the backward input signal path.
There are also some issues which need to be considered in
protecting the P82B96 from spurious signals in a bus line installed
over a long distance, or where signals may be picked up which
exceed the supply rail levels.
INTERFACING DIFFERENT SUPPLY/LOGIC
2
The fixed, low, logic levels used at Sx imply a restriction that the I C
LEVELS
2
bus connection on this chip should be used only with small I C
Figure 1 shows P82B96 applied with the I/O pins Tx and Rx linked
2
systems, contained typically on one printed circuit board, and not
connected with long wiring which could introduce noise.
to provide a new bus with the same protocol and properties as I C
but operating at different logic levels. Because Tx has an open
collector output a pull-up resistor is applied.
It is the intention that the P82B96 be used as an interface to long or
2
noisy bus systems so that the function of each local I C bus node
Supply voltages in the range 2 V to 15 V are permitted, allowing
remains within specification, and the P82B96 handles the more
difficult interfacing tasks.
2
interfacing from a conventional 5 V I C bus to 3 V logic systems or
low current bus systems such as SMB with 350 µA pull-down
Series resistors in the SDA/SCL lines should also be avoided in the
Sx lines at I C nodes that include P82B96.
current. It must be remembered that the input threshold at Rx on the
2
buffered bus side is nominally at one half of the V voltage.
CC
A further implication of the way in which the P82B96 functions is that
if two P82B96 chips have their Sx pins connected to the same I C
node, then signals from the Rx input of one P82B96 will not
propagate to Tx on the other. This is dictated by the non-latching
requirement that they must not propagate back to Tx within one
chip.
Hence longer cable runs and ground potential differences can be
accommodated by using a 15 V supply to improve noise immunity
while retaining the simplicity of I C wiring.
2
2
The oscilloscope traces, Figures 2 and 3, show the waveforms at
Tx, Rx, and Sx when Tx is not linked to Rx. Tx has a 330Ω pull-up to
the chip supply of 10 V, Sx has a 1600Ω pull-up to a 5 V supply.
There is no external capacitive bus loading. The propagation delay
for signals from Sx to Tx is about 100ns, and from Rx to Sx it is
about 300ns.
As the buffered output of the P82B96 has increased drive capability
2
over the normal I C specification, these limitations do not present
any great restriction. The buffered side can be used for
interconnection, and distance.
+V (2–15 V)
CC
+5 V
R1
2
I C
SDA
‘SDA’
(NEW LEVELS)
Tx
(SDA)
Rx
(SDA)
1/2 PB2B96
NOTE: The logic voltages and currents at ‘SDA’ are set by V and pull-up.
CC
EXAMPLE: ‘SMB’ bus l = 350 mA, use V = 5 V and pull-up R1 = 13 KW
SU01021
low
CC
2
Figure 1. Interfacing an “I C” type of bus with different logic levels
ch1: freq = 624 kHz
ch1: freq = 624 kHz
Rx
Tx
10V
Sx
5V
Sx
0V
CH1!2.00V = AVG
CH2!2.00V = BWL MTB 200ns – 0.98dvch1+
CH1!2.00V = AVG
CH2!2.00V = BWL MTB 200ns – 0.98dvch1+
SU01069
Horiz: 200ns/div. VertL 2V/div.
SU01070
Horiz: 200ns/div. VertL 2V/div.
Figure 2. Propagation Sx to Tx
Figure 3. Propagation Rx to Sx
Sx pull-up to 5V, V = 10V
Sx pull-up to 5V, Tx pull-up to V = 10V
CC
CC
2
2001 Feb 14
5秒后页面跳转
STM32H743技术深度剖析与应用案例探索
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
74HC14芯片资料介绍：性能特性分析、引脚介绍
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
