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AFE1115E/1K PDF预览

AFE1115E/1K

更新时间: 2024-10-28 20:00:39
品牌 Logo 应用领域
德州仪器 - TI 电信光电二极管电信集成电路
页数 文件大小 规格书
14页 168K
描述
DATACOM, DIGITAL SLIC, PDSO56, PLASTIC, SSOP-56

AFE1115E/1K 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP, SSOP56,.4
针数:56Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.75
数据速率:1168 MbpsJESD-30 代码:R-PDSO-G56
JESD-609代码:e0长度:18.415 mm
湿度敏感等级:3功能数量:1
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP56,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):220电源:3.3/5,5 V
认证状态:Not Qualified座面最大高度:2.794 mm
子类别:Other Telecom ICs标称供电电压:3.3 V
表面贴装:YES技术:CMOS
电信集成电路类型:DIGITAL SLIC温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
Base Number Matches:1

AFE1115E/1K 数据手册

 浏览型号AFE1115E/1K的Datasheet PDF文件第8页浏览型号AFE1115E/1K的Datasheet PDF文件第9页浏览型号AFE1115E/1K的Datasheet PDF文件第10页浏览型号AFE1115E/1K的Datasheet PDF文件第12页浏览型号AFE1115E/1K的Datasheet PDF文件第13页浏览型号AFE1115E/1K的Datasheet PDF文件第14页 
13.5dBm delivered to the line; and a pseudo-random  
equiprobable sequence of HDSL pulses. The power dissipa-  
tion specifications includes all power dissipated in the  
AFE1115, it does not include power dissipated in the exter-  
sible. The placement of the Tantalum capacitor is not as  
critical, but should be close to the pin. In each case, the  
capacitor should be connected between AVDD and AGND  
(pins 49 and 50). The capacitors should be placed in quiet  
analog areas rather than noisy digital areas.  
nal  
load.  
The external power is 16.5dBm, 13.5dBm to the line and  
13.5dBm to the impedance matching resistors. The external  
load power of 16.5dBm is 45mW. The typical power dissi-  
pation in the AFE1115 under various conditions is shown in  
In most systems, it will be natural to derive AVDD for the  
phase-locked loop (PLL) from the AVDD supply. A 5to  
10resistor should be used to connect PLL AVDD (pin 49)  
to the analog supply. This resistor in combination with the  
10µF capacitor form a lowpass filter—keeping glitches on  
the analog supply from affecting the phase locked loop.  
Ideally, the phase-locked loop power supply would originate  
from the analog supply (via the 5to 10resistor) near the  
power connector for the printed circuit board. Likewise, the  
PLL ground should connect to a large PCB trace or small  
ground plane which returns to the power supply connector  
underneath the PLL AVDD supply path. The PLL “ground  
plane” should also extend underneath PLLIN and PLLOUT  
(pins 51 and 52).  
TYPICAL POWER  
BIT RATE  
PER AFE1115  
(Symbols/sec)  
DISSIPATION  
IN THE AFE1115  
(mW)  
DVDD  
(V)  
1168 (E1)  
1168 (E1)  
784 (T1)  
784 (T1)  
292 (1/4 E1)  
292 (1/4 E1)  
3.3  
5
3.3  
5
3.3  
5
300  
350  
290  
330  
280  
300  
TABLE IV. Typical Power Dissipation.  
The remaining portion of the AFE1115 should be considered  
analog. The four non-PLL AGND pins (pins 36, 37, 42, and  
46) should be connected directly to a common analog  
ground plane and all non-PLL AVDD pins should be con-  
nected to an analog 5V power plane. Both of these planes  
should have a low impedance path to the power supply.  
Table IV.  
LAYOUT  
The analog front end of an HDSL system has a number of  
conflicting requirements. It must accept and deliver digital  
outputs at fairly high rates of speed, generate a VCXO clock,  
phase-lock to a high-speed digital clock, and convert the line  
input to a high-precision (14-bit) digital output. Thus, there  
are really four sections of the AFE1115: the digital section,  
the phase-locked loop, the VCXO and the analog section.  
Ideally, all ground planes and traces and all power planes  
and traces should return to the power supply connector  
before being connected together (if necessary). Each ground  
and power pair should be routed over each other, should not  
overlap any portion of another pair, and the pairs should be  
separated by a distance of at least 0.25 inch (6mm). One  
exception is that the digital and analog ground planes should  
be connected together underneath the AFE1115 by a small  
trace.  
DIGITAL LAYOUT  
The power supply for the digital section of the AFE1115 can  
range from 3.3V to 5V. This supply should be decoupled to  
digital ground with a ceramic 0.1µF capacitor placed as  
close as possible to digital ground (DGND, pin 16) and  
digital power (DVDD, pin 17). Ideally, both a digital power  
supply plane and a digital ground plane should run to and  
underneath the digital pins of the AFE1115 (pins 7 through  
30). However, DVDD may be supplied by a wide printed  
circuit board trance. A digital ground plane underneath all  
digital pins is strongly recommended. The VCXO circuit  
needs special attention for layout. There is a portion of the  
external VCXO circuitry which needs to be as far away as  
possible from a ground or power plane or other traces. See  
the discussion below in the section titled VCXO Circuit and  
Layout.  
VCXO CIRCUIT AND LAYOUT  
The VCXO circuitry is shown in Figure 7. The basic VCXO  
circuit consists of on-chip control DAC, amplifiers, Schmidt  
triggers, and clock buffer along with an external crystal and  
varactor diodes. The control DAC output (vcDAC) varies  
the capacitance of the varactor diodes (D1 and D2), which  
controls the frequency at which the crystal circuit oscillates.  
The buffered clock output is available at pin 3, VCXO Clock  
Output.  
Important Note: To achieve specified analog performance  
when using VCXO, the crystal frequency of the VCXO must  
be 48x the baud rate. In addition, the txCLK and the  
rxSYNC control signals must be derived from the VCXO  
clock so that the edges of the control signal are synchronized  
with the 48x crystal frequency. If these recommendations  
are followed, the key internal analog decisions are made at  
the time of minimum noise. As an example, for an E1 rate  
of 1168kbps, the symbol rate is 584k symbols per second. In  
this case the VCXO crystal frequency should be 48 x 584k  
= 28.032MHz. Likewise, for T1, the crystal frequency should  
be 18.816MHz.  
ANALOG LAYOUT  
The phase-locked loop is powered from AVDD (pin 50) and  
its ground is referenced to AGND (pin 49). Note that AVDD  
must be in the 4.75V to 5.25V range. This portion of the  
AFE1115 should be decoupled with both 10µF Tantalum  
capacitor and a 0.1µF ceramic capacitor. The ceramic ca-  
pacitor should be placed as close to the AFE1115 as pos-  
®
11  
AFE1115  

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