5秒后页面跳转
捷配首页

Datasheet > ADF4355-3BCPZ-RL7
ADF4355-3BCPZ-RL7 PDF预览

ADF4355-3BCPZ-RL7

更新时间： 2024-02-25 15:19:08
品牌 Logo 应用领域
亚德诺 - ADI 输入元件信息通信管理
页数 文件大小 规格书
35页 917K
描述
Microwave Wideband Synthesizer with Integrated VCO

阅读下载

中文翻译

获取价格

ADF4355-3BCPZ-RL7 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active包装说明：HVQCCN,
针数：32Reach Compliance Code：compliant
风险等级：5.68其他特性：INPUT FREQUENCY IN SINGLE-ENDED MODE 250MHZ; WHEN DOUBLER ENABLED= 100MHZ
模拟集成电路 - 其他类型：PHASE LOCKED LOOPJESD-30 代码：S-XQCC-N32
JESD-609代码：e3长度：5 mm
湿度敏感等级：3功能数量：1
端子数量：32最高工作温度：105 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
座面最大高度：0.8 mm最大供电电压 (Vsup)：3.4485 V
最小供电电压 (Vsup)：3.1515 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：5 mmBase Number Matches：1

ADF4355-3BCPZ-RL7 数据手册

 浏览型号ADF4355-3BCPZ-RL7的Datasheet PDF文件第5页浏览型号ADF4355-3BCPZ-RL7的Datasheet PDF文件第6页浏览型号ADF4355-3BCPZ-RL7的Datasheet PDF文件第7页浏览型号ADF4355-3BCPZ-RL7的Datasheet PDF文件第9页浏览型号ADF4355-3BCPZ-RL7的Datasheet PDF文件第10页浏览型号ADF4355-3BCPZ-RL7的Datasheet PDF文件第11页 
Data Sheet  
ADF4355-3  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
CLK  
DATA  
LE  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
V
V
BIAS  
REF  
R
A
V
SET  
ADF4355-3  
TOP VIEW  
(Not to Scale)  
CE  
GNDVCO  
TUNE  
AV  
DD  
V
P
OUT  
V
A
V
REGVCO  
CP  
GNDVCO  
VCO  
CP  
GND  
NOTES  
1. THE EXPOSED PAD MUST BE CONNECTED TO A  
.
GND  
Figure 3. Pin Configuration  
Table 4. Pin Function Descriptions  
Pin No. Mnemonic Description  
1
CLK  
DATA  
LE  
Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high  
impedance CMOS input.  
Serial Data Input. The serial data is loaded most significant bit (MSB) first with the four least significant bits (LSBs)  
as the control bits. This input is a high impedance CMOS input.  
Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register that  
is selected by the four LSBs.  
2
3
4
CE  
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode. A  
logic high on this pin powers up the device, depending on the status of the power-down bits.  
5, 16  
AVDD  
VP  
Analog Power Supplies. These pins range from 3.1515 V to 3.4485 V. Connect decoupling capacitors to the analog  
ground plane as close to these pins as possible. AVDD must have the same value as DVDD.  
Charge Pump Power Supply. VP must have the same value as VVCO. Connect decoupling capacitors to the ground  
plane as close to this pin as possible.  
Charge Pump Output. When enabled, this output provides ICP to the external loop filter. The output of the loop  
filter is connected to VTUNE to drive the internal VCO.  
6
7
CPOUT  
8
9
10  
CPGND  
AGND  
VRF  
Charge Pump Ground. This output is the ground return pin for CPOUT.  
Analog Ground. Ground return pin for AVDD.  
Power Supply for the RF Output. Connect decoupling capacitors to the analog ground plane as close to this pin  
as possible. VRF must have the same value as AVDD. For optimum spurious performance, VRF and DVDD must  
originate from different regulators.  
11  
12  
RFOUTA+  
RFOUTA−  
VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is available.  
Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided down  
version is available.  
13  
14  
AGNDRF  
RFOUTB+  
RF Output Stage Ground. This pin is the ground return for the RF output stage.  
Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a divided down version  
is available.  
15  
17  
RFOUTB−  
VVCO  
Complementary Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a  
divided down version is available.  
Power Supply for the VCO. The voltage on this pin ranges from 3.1515 V to 3.4485 V. Connect decoupling  
capacitors to the analog ground plane as close to this pin as possible.  
18, 21  
19  
AGNDVCO  
VREGVCO  
VCO Ground. This pin is the ground return path for the VCO.  
VCO Compensation Node. Connect decoupling capacitors to the ground plane as close to this pin as possible.  
Connect this pin directly to VVCO  
.
20  
VTUNE  
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CPOUT  
output voltage. The capacitance at this pin (VTUNE input capacitance) is 7 pF.  
Rev. B | Page 7 of 34  
 
1...567891011...35

中文翻译

下载PDF

ADF4355-3BCPZ-RL7 替代型号

型号 品牌 替代类型 描述 数据表
ADF4355-3BCPZ ADI

完全替代

 Microwave Wideband Synthesizer with Integrated VCO

与ADF4355-3BCPZ-RL7相关器件

型号 品牌 获取价格 描述 数据表
ADF4355BCPZ ADI

获取价格

 		Microwave Wideband Synthesizer with Integrated VCO
ADF4355BCPZ-RL7 ADI

获取价格

 		Microwave Wideband Synthesizer with Integrated VCO
ADF4356 ADI

获取价格

 		6.8 GHz Wideband Synthesizer with Integrated VCO
ADF4356_17 ADI

获取价格

 		6.8 GHz Wideband Synthesizer with Integrated VCO
ADF4356BCPZ ADI

获取价格

 		6.8 GHz Wideband Synthesizer with Integrated VCO
ADF4356BCPZ-RL7 ADI

获取价格

 		6.8 GHz Wideband Synthesizer with Integrated VCO
ADF4360-0 ADI

获取价格

 		Integrated Synthesizer and VCO
ADF4360-0BCP ADI

获取价格

 		Integrated Synthesizer and VCO
ADF4360-0BCPRL ADI

获取价格

 		Integrated Synthesizer and VCO
ADF4360-0BCPRL7 ADI

获取价格

 		Integrated Synthesizer and VCO

与ADF4355-3BCPZ-RL7相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证