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ADF4355-3BCPZ-RL7 PDF预览

ADF4355-3BCPZ-RL7

更新时间： 2024-02-16 20:47:05
品牌 Logo 应用领域
亚德诺 - ADI 输入元件信息通信管理
页数 文件大小 规格书
35页 917K
描述
Microwave Wideband Synthesizer with Integrated VCO

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ADF4355-3BCPZ-RL7 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active包装说明：HVQCCN,
针数：32Reach Compliance Code：compliant
风险等级：5.68其他特性：INPUT FREQUENCY IN SINGLE-ENDED MODE 250MHZ; WHEN DOUBLER ENABLED= 100MHZ
模拟集成电路 - 其他类型：PHASE LOCKED LOOPJESD-30 代码：S-XQCC-N32
JESD-609代码：e3长度：5 mm
湿度敏感等级：3功能数量：1
端子数量：32最高工作温度：105 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
座面最大高度：0.8 mm最大供电电压 (Vsup)：3.4485 V
最小供电电压 (Vsup)：3.1515 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：5 mmBase Number Matches：1

ADF4355-3BCPZ-RL7 数据手册

 浏览型号ADF4355-3BCPZ-RL7的Datasheet PDF文件第6页浏览型号ADF4355-3BCPZ-RL7的Datasheet PDF文件第7页浏览型号ADF4355-3BCPZ-RL7的Datasheet PDF文件第8页浏览型号ADF4355-3BCPZ-RL7的Datasheet PDF文件第10页浏览型号ADF4355-3BCPZ-RL7的Datasheet PDF文件第11页浏览型号ADF4355-3BCPZ-RL7的Datasheet PDF文件第12页 
ADF4355-3  
Data Sheet  
Pin No. Mnemonic  
Description  
22  
23  
RSET  
VREF  
Bias Current Resistor. Connecting a resistor between this pin and ground sets the charge pump output current.  
Internal Compensation Node. VREF is dc biased at half of the tuning range. Connect decoupling capacitors to the  
ground plane as close to this pin as possible. The recommended capacitor values are 10 pF, 1 nF, and 4.7 µF.  
24  
VBIAS  
Reference Voltage. Connect decoupling capacitors to the ground plane as close to this pin as possible. The  
recommended capacitor values are 10 pF, 1 nF, and 1 µF.  
25, 32  
CREG1, CREG  
2
Outputs from the LDO Regulator. Pin 25 and Pin 32 are the supply voltages to the digital circuits, and have a  
nominal voltage of 1.8 V. Decoupling capacitors of 100 nF connected to AGND are required for these pins.  
26  
27  
PDBRF  
DVDD  
RF Power-Down. A logic low on this pin mutes the RF outputs. This mute function is also software-controllable.  
Digital Power Supply. This pin must be at the same voltage as AVDD. Place decoupling capacitors to the ground  
plane as close to this pin as possible. For optimum spurious performance, VRF and DVDD must originate from  
different regulators.  
28  
29  
30  
REFINB  
REFINA  
MUXOUT  
Complementary Reference Input. If unused, ac-couple this pin to AGND  
Reference Input.  
Multiplexer Output. The multiplexer output allows the digital lock detect, the analog lock detect, scaled RF, or the  
scaled reference frequency to be externally accessible.  
.
31  
SDGND  
EP  
Digital Σ-Δ Modulator Ground. Pin 31 is the ground return path for the Σ-Δ modulator.  
Exposed Pad. The exposed pad must be connected to AGND  
.
Rev. B | Page 8 of 34  
1...6789101112...35

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